Uygar E. Avci
Uygar E. Avci
Components Research, Intel Corp.
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Tunnel field-effect transistors: Prospects and challenges
UE Avci, DH Morris, IA Young
IEEE Journal of the Electron Devices Society 3 (3), 88-95, 2015
Comparison of performance, switching energy and process variations for the TFET and MOSFET in logic
UE Avci, R Rios, K Kuhn, IA Young
2011 Symposium on VLSI Technology-Digest of Technical Papers, 124-125, 2011
Floating body cell with independently-controlled double gates for high density memory
I Ban, UE Avci, U Shah, CE Barns, DL Kencke, P Chang
2006 International Electron Devices Meeting, 1-4, 2006
Scaled TFET transistor formed using nanowire with surface termination
UE Avci, R Rios, KJ Kuhn, IA Young, JR Weber
US Patent 10,535,770, 2020
Floating body memory cell having gates favoring different conductivity type regions
PLD Chang, UE Avci, DL Kencke, I Ban
US Patent 8,217,435, 2012
Bandgap engineering of group IV materials for complementary n and p tunneling field effect transistors
R Kotlyar, UE Avci, S Cea, R Rios, TD Linton, KJ Kuhn, IA Young
Applied Physics Letters 102 (11), 113106, 2013
Design of low voltage tunneling-FET logic circuits considering asymmetric conduction characteristics
DH Morris, UE Avci, R Rios, IA Young
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 4 (4 …, 2014
Heterojunction TFET scaling and resonant-TFET for steep subthreshold slope at sub-9nm gate-length
UE Avci, IA Young
2013 IEEE International Electron Devices Meeting, 4.3. 1-4.3. 4, 2013
The ultimate CMOS device and beyond
KJ Kuhn, U Avci, A Cappellani, MD Giles, M Haverty, S Kim, R Kotlyar, ...
2012 International Electron Devices Meeting, 8.1. 1-8.1. 4, 2012
Energy efficiency comparison of nanowire heterojunction TFET and Si MOSFET at Lg=13nm, including P-TFET and variation considerations
UE Avci, DH Morris, S Hasan, R Kotlyar, R Kim, R Rios, DE Nikonov, ...
2013 IEEE International Electron Devices Meeting, 33.4. 1-33.4. 4, 2013
Understanding the feasibility of scaled III–V TFET for logic by bridging atomistic simulations and experimental results
UE Avci, S Hasan, DE Nikonov, R Rios, K Kuhn, IA Young
2012 Symposium on VLSI Technology (VLSIT), 183-184, 2012
Physical origin of transient negative capacitance in a ferroelectric capacitor
SC Chang, UE Avci, DE Nikonov, S Manipatruni, IA Young
Physical Review Applied 9 (1), 014010, 2018
Source/drain doping effects and performance analysis of ballistic III-V n-MOSFETs
R Kim, UE Avci, IA Young
IEEE Journal of the Electron Devices Society 3 (1), 37-43, 2014
CMOS performance benchmarking of Si, InAs, GaAs, and Ge nanowire n-and pMOSFETs with Lg= 13 nm based on atomistic quantum transport simulation including strain effects
R Kim, UE Avci, IA Young
2015 IEEE International Electron Devices Meeting (IEDM), 34.1. 1-34.1. 4, 2015
Study of TFET non-ideality effects for determination of geometry and defect density requirements for sub-60mV/dec Ge TFET
UE Avci, B Chu-Kung, A Agrawal, G Dewey, V Le, R Rios, DH Morris, ...
2015 IEEE International Electron Devices Meeting (IEDM), 34.5. 1-34.5. 4, 2015
Comprehensive performance benchmarking of III-V and Si nMOSFETs (gate length= 13 nm) considering supply voltage and OFF-current
R Kim, UE Avci, IA Young
IEEE Transactions on Electron Devices 62 (3), 713-721, 2015
Comparison of power and performance for the TFET and MOSFET and considerations for P-TFET
UE Avci, R Rios, KJ Kuhn, IA Young
2011 11th IEEE International Conference on Nanotechnology, 869-872, 2011
Floating body cell (FBC) memory for 16-nm technology with low variation on thin silicon and 10-nm BOX
UE Avci, I Ban, DL Kencke, PLD Chang
2008 IEEE International SOI Conference, 29-30, 2008
A scaled floating body cell (FBC) memory with high-k+ metal gate on thin-silicon and thin-BOX for 16-nm technology node and beyond
I Ban, UE Avci, DL Kencke, PLD Chang
2008 Symposium on VLSI Technology, 92-93, 2008
Field effect transistors having ferroelectric or antiferroelectric gate dielectric structure
S Kim, UE Avci, JM Howard, IA Young, DH Morris
US Patent App. 16/635,739, 2020
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