Ashish Agrawal
Ashish Agrawal
Devcie Engineer at Components Research, Intel Corporation
Verified email at - Homepage
Cited by
Cited by
A steep-slope transistor based on abrupt electronic phase transition
N Shukla, AV Thathachary, A Agrawal, H Paik, A Aziz, DG Schlom, ...
Nature communications 6 (1), 7812, 2015
Transistor source/drain amorphous interlayer arrangements
A Agrawal, B Chu-Kung, SH Sung, S Chouksey, GA Glass, VH Le, ...
US Patent App. 16/347,110, 2019
Effect of phosphate solubilizing bacteria on the germination of Cicer arietinum seeds and seedling growth
K Sharma, G Dak, A Agrawal, M Bhatnagar, R Sharma
Journal of Herbal Medicine and Toxicology 1 (1), 61-63, 2007
300mm heterogeneous 3D integration of record performance layer transfer germanium PMOS with silicon NMOS for low power high performance logic applications
W Rachmady, A Agrawal, SH Sung, G Dewey, S Chouksey, B Chu-Kung, ...
2019 IEEE International Electron Devices Meeting (IEDM), 29.7. 1-29.7. 4, 2019
Fermi level depinning and contact resistivity reduction using a reduced titania interlayer in n-silicon metal-insulator-semiconductor ohmic contacts
A Agrawal, J Lin, M Barth, R White, B Zheng, S Chopra, S Gupta, K Wang, ...
Applied Physics Letters 104 (11), 2014
Experimental staggered-source and N+ pocket-doped channel III–V tunnel field-effect transistors and their scalabilities
D Mohata, S Mookerjea, A Agrawal, Y Li, T Mayer, V Narayanan, A Liu, ...
Applied physics express 4 (2), 024105, 2011
A unified model for insulator selection to form ultra-low resistivity metal-insulator-semiconductor contacts to n-Si, n-Ge, and n-InGaAs
A Agrawal, N Shukla, K Ahmed, S Datta
Applied Physics Letters 101 (4), 2012
Study of TFET non-ideality effects for determination of geometry and defect density requirements for sub-60mV/dec Ge TFET
UE Avci, B Chu-Kung, A Agrawal, G Dewey, V Le, R Rios, DH Morris, ...
2015 IEEE International Electron Devices Meeting (IEDM), 34.5. 1-34.5. 4, 2015
Gate-All-Around Strained Si0.4Ge0.6 Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application
A Agrawal, S Chouksey, W Rachmady, S Vishwanath, S Ghose, M Mehta, ...
2020 IEEE International Electron Devices Meeting (IEDM), 2.2. 1-2.2. 4, 2020
Critical discussion on (100) and (110) orientation dependent transport: nMOS planar and FinFET
CD Young, MO Baykan, A Agrawal, H Madan, K Akarvardar, C Hobbs, ...
2011 Symposium on VLSI Technology-Digest of Technical Papers, 18-19, 2011
Advanced composite high-κ gate stack for mixed anion arsenide-antimonide quantum well transistors
A Ali, H Madan, R Misra, E Hwang, A Agrawal, I Ramirez, P Schiffer, ...
2010 International Electron Devices Meeting, 6.3. 1-6.3. 4, 2010
Barrier height reduction to 0.15eV and contact resistivity reduction to 9.1×10−9 Ω-cm2 using ultrathin TiO2−x interlayer between metal and silicon
A Agrawal, J Lin, B Zheng, S Sharma, S Chopra, K Wang, A Gelatos, ...
2013 Symposium on VLSI Technology, T200-T201, 2013
Experimental determination of quantum and centroid capacitance in arsenide–antimonide quantum-well MOSFETs incorporating nonparabolicity effect
A Ali, H Madan, R Misra, A Agrawal, P Schiffer, JB Boos, BR Bennett, ...
IEEE transactions on electron devices 58 (5), 1397-1403, 2011
Enhancement-mode antimonide quantum-well MOSFETs with high electron mobility and gigahertz small-signal switching performance
A Ali, H Madan, A Agrawal, I Ramirez, R Misra, JB Boos, BR Bennett, ...
IEEE electron device letters 32 (12), 1689-1691, 2011
Heterogeneous integration of hexagonal boron nitride on bilayer quasi‐free‐standing epitaxial graphene and its impact on electrical transport properties
MJ Hollander, A Agrawal, MS Bresnehan, M LaBella, KA Trumbull, ...
physica status solidi (a) 210 (6), 1062-1070, 2013
Enhancement mode strained (1.3%) germanium quantum well FinFET (WFin=20nm) with high mobility (μHole=700 cm2/Vs), low EOT (∼0.7nm) on bulk silicon …
A Agrawal, M Barth, GB Rayner, VT Arun, C Eichfeld, G Lavallee, SY Yu, ...
2014 IEEE International Electron Devices Meeting, 16.4. 1-16.4. 4, 2014
Highly-stable (< 3% fluctuation) Ag-based threshold switch with extreme-low OFF current of 0.1 pA, extreme-high selectivity of 10 9 and high endurance of 10 9 cycles
W Banerjee, IV Karpov, A Agrawal, S Kim, S Lee, S Lee, D Lee, H Hwang
2020 IEEE International Electron Devices Meeting (IEDM), 28.4. 1-28.4. 4, 2020
Gate-all-around strained Si
A Agrawal, S Chouksey, W Rachmady, S Vishwanath, S Ghose, M Mehta
IEDM Tech. Dig, 2.2, 2020
In Situ Process Control of Trilayer Gate-Stacks on p-Germanium With 0.85-nm EOT
YX Zheng, A Agrawal, GB Rayner, MJ Barth, K Ahmed, S Datta, ...
IEEE Electron Device Letters 36 (9), 881-883, 2015
A steep-slope transistor based on abrupt electronic phase transition Nat
N Shukla, AV Thathachary, A Agrawal, H Paik, A Aziz, DG Schlom, ...
Commun 6, 7812, 2015
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