| A study of DRAM failures in the field V Sridharan, D Liberty SC'12: Proceedings of the International Conference on High Performance …, 2012 | 233 | 2012 |
| A study of DRAM failures in the field V Sridharan, D Liberty SC'12: Proceedings of the International Conference on High Performance …, 2012 | 233 | 2012 |
| Memory errors in modern systems: The good, the bad, and the ugly V Sridharan, N DeBardeleben, S Blanchard, KB Ferreira, J Stearley, ... ACM SIGARCH Computer Architecture News 43 (1), 297-310, 2015 | 206 | 2015 |
| Feng shui of supercomputer memory positional effects in DRAM and SRAM faults V Sridharan, J Stearley, N DeBardeleben, S Blanchard, S Gurumurthi SC'13: Proceedings of the International Conference on High Performance …, 2013 | 161 | 2013 |
| Eliminating microarchitectural dependency from architectural vulnerability V Sridharan, DR Kaeli 2009 IEEE 15th International Symposium on High Performance Computer …, 2009 | 153 | 2009 |
| Balancing performance and reliability in the memory hierarchy GH Asadi, VS Mehdi, B Tahoori, D Kaeli IEEE International Symposium on Performance Analysis of Systems and Software …, 2005 | 109 | 2005 |
| Using hardware vulnerability factors to enhance AVF analysis V Sridharan, DR Kaeli ACM SIGARCH Computer Architecture News 38 (3), 461-472, 2010 | 73 | 2010 |
| Reducing data cache susceptibility to soft errors V Sridharan, H Asadi, MB Tahoori, D Kaeli IEEE Transactions on Dependable and Secure Computing 3 (4), 353-364, 2006 | 64 | 2006 |
| Reducing data cache susceptibility to soft errors V Sridharan, H Asadi, MB Tahoori, D Kaeli IEEE Transactions on Dependable and Secure Computing 3 (4), 353-364, 2006 | 64 | 2006 |
| Resilient die-stacked DRAM caches J Sim, GH Loh, V Sridharan, M O'Connor ACM SIGARCH Computer Architecture News 41 (3), 416-427, 2013 | 59 | 2013 |
| Vulnerability analysis of L2 cache elements to single event upsets H Asadi, V Sridharan, MB Tahoori, D Kaeli Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 59 | 2006 |
| Real-world design and evaluation of compiler-managed GPU redundant multithreading J Wadden, A Lyashevsky, S Gurumurthi, V Sridharan, K Skadron ACM SIGARCH Computer Architecture News 42 (3), 73-84, 2014 | 52 | 2014 |
| Low-power, low-storage-overhead chipkill correct via multi-line error correction X Jian, H Duwe, J Sartori, V Sridharan, R Kumar Proceedings of the International Conference on High Performance Computing …, 2013 | 45 | 2013 |
| Quantifying software vulnerability V Sridharan, DR Kaeli Proceedings of the 2008 workshop on Radiation effects and fault tolerance in …, 2008 | 45 | 2008 |
| Design and Analysis of an APU for Exascale Computing T Vijayaraghavan, Y Eckert, GH Loh, MJ Schulte, M Ignatowski, ... 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 42 | 2017 |
| Calculating architectural vulnerability factors for spatial multi-bit transient faults M Wilkening, V Sridharan, S Li, F Previlon, S Gurumurthi, DR Kaeli 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 293-305, 2014 | 39 | 2014 |
| XED: Exposing on-die error detection information for strong memory reliability PJ Nair, V Sridharan, MK Qureshi 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture …, 2016 | 33 | 2016 |
| Detecting and correcting hard errors in a memory array J Kalamatianos, JK John, R Gelinas, VK Sridharan, PE Nevius US Patent 9,189,326, 2015 | 30 | 2015 |
| The effect of input data on program vulnerability V Sridharan, DR Kaeli Workshop on System Effects of Logic Soft Errors (SELSE-5), 2009 | 25 | 2009 |
| Using pvf traces to accelerate avf modeling V Sridharan, DR Kaeli Proceedings of the IEEE workshop on silicon errors in logic-system effects …, 2010 | 21 | 2010 |
