| Lowering power consumption in clock by using globally asynchronous locally synchronous design style A Hemani, T Meincke, S Kumar, A Postula, T Olsson, P Nilsson, J Oberg, ... Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 873-878, 1999 | 226 | 1999 |
| Hardware/software partitioning and minimizing memory interface traffic A Jantsch, P Ellervee, A Hemani, J Öberg, H Tenhunen European Design Automation Conference: Proceedings of the conference on …, 1994 | 142 | 1994 |
| A case study on hardware/software partitioning A Jantsch, P Ellervee, J Oberg, A Hemani Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines, 111-118, 1994 | 97 | 1994 |
| Globally asynchronous locally synchronous architecture for large high-performance ASICs T Meincke, A Hemani, S Kumar, P Ellervee, J Oberg, T Olsson, P Nilsson, ... 1999 IEEE International Symposium on Circuits and Systems (ISCAS) 2, 512-515, 1999 | 61 | 1999 |
| System level power-performance trade-offs in embedded systems using voltage and frequency scaling of off-chip buses and memory K Puttaswamy, KW Choi, JC Park, VJ Mooney III, A Chatterjee, P Ellervee Proceedings of the 15th international symposium on System Synthesis, 225-230, 2002 | 34 | 2002 |
| A fast algorithm for three-level logic optimization E Dubrova, P Ellervee Proc. Int. Workshop on Logic Synthesis, 251-254, 1999 | 29 | 1999 |
| A software oriented approach to hardware/software codesign A Jantsch, P Ellervee, J Oberg, A Hemani, H Tenhunen Proc. of the Poster Session of CC 94, 1994 | 24 | 1994 |
| FPGA-based fault emulation of synchronous sequential circuits P Ellervee, J Raik, K Tammemäe, RJ Ubar IET Computers & Digital Techniques 1 (2), 70-76, 2007 | 22 | 2007 |
| FPGA-based fault emulation of synchronous sequential circuits P Ellervee, J Raik, K Tammemäe, RJ Ubar IET Computers & Digital Techniques 1 (2), 70-76, 2007 | 22 | 2007 |
| Fast RTL fault simulation using decision diagrams and bitwise set operations U Reinsalu, J Raik, R Ubar, P Ellervee 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2011 | 20 | 2011 |
| Code coverage analysis using high-level decision diagrams J Raik, U Reinsalu, R Ubar, M Jenihhin, P Ellervee 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and …, 2008 | 19 | 2008 |
| Method and apparatus for encoding/decoding n-bit data into 2n-bit codewords A Djupsjöbacka, P Ellervee, M Mokhtari US Patent 6,232,895, 2001 | 19 | 2001 |
| Method and apparatus for encoding/decoding n-bit data into 2n-bit codewords A Djupsjöbacka, P Ellervee, M Mokhtari US Patent 6,232,895, 2001 | 19 | 2001 |
| High-level synthesis of control and memory intensive applications P Ellervee Institutionen för elektronisk systemkonstruktion, 2000 | 19 | 2000 |
| Automatic synthesis of asynchronous circuits from synchronous RTL descriptions J Oberg, J Plosila, P Ellervee 2005 NORCHIP, 200-205, 2005 | 15 | 2005 |
| Evaluating benefits of globally asynchronous locally synchronous VLSI architecture T Meincke, A Hemani, P Ellervee, J Öberg, S Kumar, D Lindqvist, ... NORCHIP, 50-57, 1998 | 14 | 1998 |
| High-level decision diagram manipulations for code coverage analysis K Minakova, U Reinsalu, A Chepurov, J Raik, M Jenihhin, R Ubar, ... 2008 11th International Biennial Baltic Electronics Conference, 207-210, 2008 | 13 | 2008 |
| Hierarchical calculation of malicious faults for evaluating the fault-tolerance R Ubar, S Devadze, M Jenihhin, J Raik, G Jervan, P Ellervee 4th IEEE International Symposium on Electronic Design, Test and Applications …, 2008 | 12 | 2008 |
| System-level data format exploration for dynamically allocated data structures P Ellervee, M Miranda, F Catthoor, A Hemani Proceedings of the 37th Annual Design Automation Conference, 556-559, 2000 | 12 | 2000 |
| Microcontroller energy consumption estimation based on software analysis for embedded systems P Ruberg, K Lass, P Ellervee 2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP …, 2015 | 11 | 2015 |
