Zaid Al-Ars
Zaid Al-Ars
Professor of Computer Engineering, Delft University of Technology
Geverifieerd e-mailadres voor tudelft.nl - Homepage
TitelGeciteerd doorJaar
Functional Memory Faults: A Formal Notation and a Taxonomy.
AJ Van de Goor, Z Al-Ars
VLSI Test Symposium 18, 281-289, 2000
2082000
Testing static and dynamic faults in random access memories
S Hamdioui, Z Al-Ars, AJ Van de Goor
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 395-400, 2002
1392002
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs
Z Al-Ars, AJ Van de Goor
Proceedings Design, Automation and Test in Europe. Conference and Exhibition …, 2001
982001
Linked faults in random access memories: concept, fault models, test algorithms, and industrial results
S Hamdioui, Z Al-Ars, AJ Van De Goor, M Rodgers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004
702004
Dynamic faults in random-access-memories: Concept, fault models and tests
S Hamdioui, Z Al-Ars, AJ Van De Goor, M Rodgers
Journal of Electronic Testing 19 (2), 195-205, 2003
572003
Hardware acceleration of sequence alignment algorithms-an overview
L Hasan, Z Al-Ars, S Vassiliadis
2007 International Conference on Design & Technology of Integrated Systems …, 2007
492007
Opens and delay faults in cmos ram address decoders
S Hamdioui, Z Al-Ars, AJ Van de Goor
IEEE Transactions on Computers 55 (12), 1630-1639, 2006
462006
Approximating infinite dynamic behavior for DRAM cell defects
Z Al-Ars, AJ van de Goor
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 401-406, 2002
402002
Static and dynamic behavior of memory cell array spot defects in embedded DRAMs
Z Al-Ars, AJ Van De Goor
IEEE Transactions on Computers 52 (3), 293-309, 2003
382003
Heterogeneous hardware/software acceleration of the BWA-MEM DNA alignment algorithm
N Ahmed, VM Sima, E Houtgast, K Bertels, Z Al-Ars
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 240-246, 2015
362015
DRAM fault analysis and test generation
Z Al-Ars
342005
Survey of fault tolerance techniques for shared memory multicore/multiprocessor systems
H Mushtaq, Z Al-Ars, K Bertels
2011 IEEE 6th International Design and Test Workshop (IDT), 12-17, 2011
302011
An FPGA-based systolic array to accelerate the BWA-MEM genomic mapping algorithm
EJ Houtgast, VM Sima, K Bertels, Z Al-Ars
2015 International Conference on Embedded Computer Systems: Architectures …, 2015
292015
Cluster-based Apache Spark implementation of the GATK DNA analysis pipeline
H Mushtaq, Z Al-Ars
2015 IEEE International Conference on Bioinformatics and Biomedicine (BIBM …, 2015
282015
Hardware implementation of the Smith-Waterman algorithm using recursive variable expansion
L Hasan, Z Al-Ars, Z Nawaz, K Bertels
2008 3rd International Design and Test Workshop, 135-140, 2008
282008
DOPA: GPU-based protein alignment using database and memory access optimizations
L Hasan, M Kentie, Z Al-Ars
BMC research notes 4 (1), 261, 2011
272011
Maximizing systolic array efficiency to accelerate the PairHMM forward algorithm
J Peltenburg, S Ren, Z Al-Ars
2016 IEEE International Conference on Bioinformatics and Biomedicine (BIBM …, 2016
262016
FPGA acceleration of the pair-HMMs forward algorithm for DNA sequence analysis
S Ren, VM Sima, Z Al-Ars
2015 IEEE International Conference on Bioinformatics and Biomedicine (BIBM …, 2015
262015
Test set development for cache memory in modern microprocessors
Z Al-Ars, S Hamdioui, G Gaydadjiev, S Vassiliadis
IEEE transactions on very large scale integration (VLSI) systems 16 (6), 725-732, 2008
242008
Efficient software-based fault tolerance approach on multicore platforms
H Mushtaq, Z Al-Ars, K Bertels
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 921-926, 2013
232013
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