Sergej Deutsch
Sergej Deutsch
Geverifieerd e-mailadres voor intel.com
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TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test
K Chakrabarty, S Deutsch, H Thapliyal, F Ye
2012 IEEE International Reliability Physics Symposium (IRPS), 5F. 1.1-5F. 1.12, 2012
702012
Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels
S Deutsch, K Chakrabarty
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013
412013
Contactless pre-bond TSV test and diagnosis using ring oscillators and multiple voltage levels
S Deutsch, K Chakrabarty
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
382014
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks
S Deutsch, B Keller, V Chickermane, S Mukherjee, N Sood, SK Goel, ...
2012 IEEE International Test Conference, 1-10, 2012
382012
Automation of 3D-DfT insertion
S Deutsch, V Chickermane, B Keller, S Mukherjee, M Konijnenburg, ...
2011 Asian Test Symposium, 395-400, 2011
262011
Test and design-for-testability solutions for 3D integrated circuits
K Chakrabarty, M Agrawal, S Deutsch, B Noia, R Wang, F Ye
IPSJ Transactions on System LSI Design Methodology 7, 56-73, 2014
172014
Compositions and methods for detecting nucleic acids
G Weber
US Patent App. 10/387,305, 2004
172004
Massive signal tracing using on-chip DRAM for in-system silicon debug
S Deutsch, K Chakrabarty
2014 International Test Conference, 1-10, 2014
152014
Contactless pre-bond TSV fault diagnosis using duty-cycle detectors and ring oscillators
S Deutsch, K Chakrabarty
2015 IEEE International Test Conference (ITC), 1-10, 2015
142015
TSV stress-aware ATPG for 3D stacked ICs
S Deutsch, K Chakrabarty, S Panth, SK Lim
2012 IEEE 21st Asian Test Symposium, 31-36, 2012
142012
Vesuvius-3D: a 3D-DfT demonstrator
EJ Marinissen, B De Wachter, S O'Loughlin, S Deutsch, C Papameletis, ...
2014 International Test Conference, 1-10, 2014
122014
Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels
K Chakrabarty, S Deutsch
US Patent 9,482,720, 2016
102016
Data backup
DA Cane, G Palagashvili, MR Boucher, DA Carson
US Patent 7,509,356, 2009
102009
Fluid level measuring device
JM Dougherty, KS Slabaugh, S Marek
US Patent 6,988,403, 2006
102006
Software-based self-test and diagnosis using on-chip memory
S Deutsch, K Chakrabarty
US Patent 9,864,007, 2018
72018
Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs
S Deutsch, K Chakrabarty, EJ Marinissen
2013 IEEE International Test Conference (ITC), 1-10, 2013
72013
Memory integrity with error detection and correction
DM Durham, S Chhabra, S Deutsch, M Long, ATN Trivedi
US Patent 9,990,249, 2018
62018
Robust optimization of test-access architectures under realistic scenarios
S Deutsch, K Chakrabarty, EJ Marinissen
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
52015
Robust optimization of test-architecture designs for core-based SoCs
S Deutsch, K Chakrabarty
2013 18th IEEE European Test Symposium (ETS), 1-6, 2013
52013
Convolutional Memory Integrity
D Durham, S Chhabra, M Kounavis, S Deutsch, K Grewal, J Cihula, ...
US Appl, 0
4
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Artikelen 1–20