| Clock domain test isolation JC Meirlevede, GAA Bos, JAM Jacobs, GEA Lousberg US Patent 6,131,173, 2000 | 25 | 2000 |
| Electronic device H Vermeulen, T Waayers, G Lousberg US Patent App. 10/245,489, 2003 | 21 | 2003 |
| Test arrangement for assemblages of intergrated circuit blocks HGH Vermeulen, TF Waayers, GEA Lousberg US Patent 6,988,230, 2006 | 17 | 2006 |
| Method of testing a memory EJ Marinissen, GEA Lousberg, P Wielage US Patent 6,829,736, 2004 | 6 | 2004 |
| Circuit with interconnect test unit FGM De Jong, MNM Muris, RMW Raaijmakers, GEA Lousberg US Patent 6,807,505, 2004 | 6 | 2004 |
| Circuit with interconnect test unit and a method of testing interconnects between a first and a second electronic circuit FGM De Jong, MNM Muris, RMW Raaijmakers, GEA Lousberg US Patent 6,622,108, 2003 | 5 | 2003 |
| Core test control JD Dingemanse, EJ Marinissen, CR Wouters, GEA Lousberg, GAA Bos, ... US Patent 6,061,284, 2000 | 5 | 2000 |
| Method and apparatus for testing a memory array using compressed responses EJ Marinissen, GEA Lousberg, P Wielage US Patent 6,721,911, 2004 | 3 | 2004 |
| Electronic circuit and method for testing AS Biewenga, LA Van De Logt, FGM De Jong, GEA Lousberg US Patent 6,883,129, 2005 | 2 | 2005 |
