Seetal Potluri
Seetal Potluri
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BioChipWork: Reverse engineering of microfluidic biochips
H Chen, S Potluri, F Koushanfar
2017 IEEE International Conference on Computer Design (ICCD), 9-16, 2017
212017
Architecture synthesis for cost-constrained fault-tolerant flow-based biochips
MC Eskesen, P Pop, S Potluri
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 618-623, 2016
102016
DFT assisted techniques for peak launch-to-capture power reduction during launch-on-shift at-speed testing
S Potluri, AS Trinadh, V Kamakoti, N Chandrachoodan
ACM Transactions on Design Automation of Electronic Systems (TODAES) 21 (1 …, 2015
92015
XStat: Statistical X-filling algorithm for peak capture power reduction in scan tests
AS Trinadh, S Potluri, S Balachandran, C Babu, V Kamakoti
Journal of Low Power Electronics 10 (1), 107-115, 2014
62014
Synthesis of on-chip control circuits for mVLSI biochips
S Potluri, A Schneider, P Pop, J Madsen
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
42017
SeqL: Secure Scan-Locking for IP Protection
S Potluri, A Aysu, A Kumar
arXiv preprint arXiv:2005.13032, 2020
32020
SeqL: SAT-attack Resilient Sequential Locking.
S Potluri, A Kumar, A Aysu
IACR Cryptol. ePrint Arch. 2019, 656, 2019
32019
Design-for-testability of on-chip control in mVLSI biochips
S Potluri, P Pop, J Madsen
IEEE Design & Test 36 (1), 48-56, 2018
32018
An efficient heuristic for peak capture power minimization during scan-based test
AS Trinadh, S Potluri, C Babu, V Kamakoti
Journal of Low Power Electronics 9 (2), 264-274, 2013
32013
Interconnect aware test power reduction
S Potluri, N Chandrachoodan, V Kamakoti
Journal of Low Power Electronics 8 (4), 516-525, 2012
32012
Microfluidic valve
S Potluri, P Pop, J Madsen, AR Schneider
WO Patent 2,018,104,516, 2018
22018
Optimal don’t care filling for minimizing peak toggles during at-speed stuck-at testing
AS Trinadh, S Potluri, V Kamakoti, SG Singh
ACM Transactions on Design Automation of Electronic Systems (TODAES) 23 (1 …, 2017
22017
LPScan: An algorithm for supply scaling and switching activity minimization during test
S Potluri, ST Adireddy, C Rajamanikkam, S Balachandran
2013 IEEE 31st International Conference on Computer Design (ICCD), 463-466, 2013
22013
Thermal-safe dynamic test scheduling method using on-chip temperature sensors for 3D MPSoCs
RK Pasumarthi, VR Devanathan, V Visvanathan, S Potluri, V Kamakoti
Journal of Low Power Electronics 8 (5), 684-695, 2012
22012
Security of microfluidic biochip: Practical attacks and countermeasures
H Chen, S Potluri, F Koushanfar
ACM Transactions on Design Automation of Electronic Systems (TODAES) 25 (3 …, 2020
12020
MLTimer: Leakage Power Minimization in Digital Circuits Using Machine Learning and Adaptive Lazy Timing Analysis
S Patanjali, M Patnaik, S Potluri, V Kamakoti
Journal of Low Power Electronics 14 (2), 285-301, 2018
12018
Cell-Aware ATPG to Improve Defect Coverage for FPGA IPs and Next Generation Zynq® MPSoCs
S Potluri, A Mathew, R Nerukonda, I Hartanto, S Toutounchi
2017 IEEE 26th Asian Test Symposium (ATS), 157-162, 2017
12017
A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips
V Gokulkrishnan, V Kamakoti, N Chandrachoodan, S Potluri
2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2017
12017
PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information
S Potluri, S Trinadh, R Baskaran, N Chandrachoodan, V Kamakoti
2013 18th IEEE European Test Symposium (ETS), 1-1, 2013
12013
Efficacy of Satisfiability Based Attacks in the Presence of Circuit Reverse Engineering Errors
Q Tan, S Potluri, A Aysu
arXiv preprint arXiv:2005.13048, 2020
2020
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Artikelen 1–20