Giorgio Di Natale
Giorgio Di Natale
CNRS - TIMA
Geverifieerd e-mailadres voor univ-grenoble-alpes.fr
TitelGeciteerd doorJaar
A novel hardware logic encryption technique for thwarting illegal overproduction and hardware trojans
S Dupuis, PS Ba, G Di Natale, ML Flottes, B Rouzeyre
2014 IEEE 20th International On-Line Testing Symposium (IOLTS), 49-54, 2014
1112014
A survey on simulation-based fault injection tools for complex systems
M Kooli, G Di Natale
2014 9th IEEE International Conference On Design & Technology of Integratedá…, 2014
672014
A watchdog processor to detect data and control flow errors
A Benso, S Di Carlo, G Di Natale, P Prinetto
9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003., 144-148, 2003
662003
An on-line BIST RAM architecture with self-repair capabilities
A Benso, S Chiusano, G Di Natale, P Prinetto
IEEE Transactions on Reliability 51 (1), 123-128, 2002
612002
Test versus security: Past and present
J Da Rolt, A Das, G Di Natale, ML Flottes, B Rouzeyre, I Verbauwhede
IEEE Transactions on Emerging topics in Computing 2 (1), 50-62, 2014
602014
Are advanced DfT structures sufficient for preventing scan-attacks?
J Da Rolt, G Di Natale, ML Flottes, B Rouzeyre
2012 IEEE 30th VLSI Test Symposium (VTS), 246-251, 2012
552012
New security threats against chips containing scan chain structures
J Da Rolt, G Di Natale, ML Flottes, B Rouzeyre
2011 IEEE International Symposium on Hardware-Oriented Security and Trustá…, 2011
542011
Control-flow checking via regular expressions
A Benso, S Di Carlo, G Di Natale, P Prinetto, L Tagliaferri
Proceedings 10th Asian Test Symposium, 299-303, 2001
502001
Scan attacks and countermeasures in presence of scan response compactors
J DaRolt, G Di Natale, ML Flottes, B Rouzeyre
2011 Sixteenth IEEE European Test Symposium, 19-24, 2011
482011
A reliable architecture for parallel implementations of the advanced encryption standard
G Di Natale, M Doulcier, ML Flottes, B Rouzeyre
Journal of Electronic Testing 25 (4-5), 269-278, 2009
482009
March AB, March AB1: new March tests for unlinked dynamic memory faults
A Benso, A Bosio, S Di Carlo, G Di Natale, P Prinetto
IEEE International Conference on Test, 2005., 8 pp.-841, 2005
452005
A programmable BIST architecture for clusters of multiple-port SRAMs
A Benso, S Di Carlo, G Di Natale, P Prinetto, ML Bodoni
Proceedings International Test Conference 2000 (IEEE Cat. No. 00CH37159á…, 2000
452000
LIFTING: A flexible open-source fault simulator
A Bosio, G Di Natale
2008 17th Asian Test Symposium, 35-40, 2008
432008
A novel differential scan attack on advanced DFT structures
JD Rolt, GD Natale, ML Flottes, B Rouzeyre
ACM Transactions on Design Automation of Electronic Systems (TODAES) 18 (4), 58, 2013
382013
Self-test techniques for crypto-devices
G Di Natale, M Doulcier, ML Flottes, B Rouzeyre
IEEE transactions on very large scale integration (VLSI) systems 18 (2), 329-333, 2009
382009
An effective distributed BIST architecture for RAMs
ML Bodoni, A Benso, S Chiusano, S Di Carlo, G Di Natale, P Prinetto
Proceedings IEEE European Test Workshop, 119-124, 2000
372000
Statistical reliability estimation of microprocessor-based systems
A Savino, S Di Carlo, G Politano, A Benso, A Bosio, G Di Natale
IEEE Transactions on Computers 61 (11), 1521-1534, 2011
362011
A new scan attack on rsa in presence of industrial countermeasures
J Da Rolt, A Das, G Di Natale, ML Flottes, B Rouzeyre, I Verbauwhede
International Workshop on Constructive Side-Channel Analysis and Secureá…, 2012
322012
Specification and design of a new memory fault simulator
A Benso, S Di Carlo, G Di Natale, P Prinetto
Proceedings of the 11th Asian Test Symposium, 2002.(ATS'02)., 92-97, 2002
312002
Static analysis of SEU effects on software applications
A Benso, S Di Carlo, G Di Natale, P Prinetto
Proceedings. International Test Conference, 500-508, 2002
312002
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Artikelen 1–20