| VLSI implementation of MIMO detection using the sphere decoding algorithm A Burg, M Borgmann, M Wenk, M Zellweger, W Fichtner, H Bolcskei IEEE Journal of solid-state circuits 40 (7), 1566-1577, 2005 | 678 | 2005 |
| Soft-output sphere decoding: Algorithms and VLSI implementation C Studer, A Burg, H Bolcskei IEEE Journal on Selected Areas in Communications 26 (2), 290-300, 2008 | 404 | 2008 |
| LLR-based successive cancellation list decoding of polar codes A Balatsoukas-Stimming, MB Parizi, A Burg IEEE transactions on signal processing 63 (19), 5165-5179, 2015 | 250 | 2015 |
| K-best MIMO detection VLSI architectures achieving up to 424 Mbps M Wenk, M Zellweger, A Burg, N Felber, W Fichtner 2006 IEEE International Symposium on Circuits and Systems, 4 pp.-1154, 2006 | 195 | 2006 |
| MIMO transmission with residual transmit-RF impairments C Studer, M Wenk, A Burg arXiv preprint arXiv:1002.0406, 2010 | 184 | 2010 |
| Prototype experience for MIMO BLAST over third-generation wireless system A Adjoudani, EC Beck, AP Burg, GM Djuknic, TG Gvoth, D Haessig, ... IEEE Journal on Selected Areas in Communications 21 (3), 440-451, 2003 | 149 | 2003 |
| VLSI implementation of a high-speed iterative sorted MMSE QR decomposition P Luethi, A Burg, S Haene, D Perels, N Felber, W Fichtner 2007 IEEE International Symposium on Circuits and Systems, 1421-1424, 2007 | 104 | 2007 |
| Hardware architecture for list successive cancellation decoding of polar codes A Balatsoukas-Stimming, AJ Raymond, WJ Gross, A Burg IEEE Transactions on Circuits and Systems II: Express Briefs 61 (8), 609-613, 2014 | 91 | 2014 |
| Design and optimization of an HSDPA turbo decoder ASIC C Benkeser, A Burg, T Cupaiuolo, Q Huang IEEE Journal of Solid-State Circuits 44 (1), 98-106, 2008 | 85 | 2008 |
| Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems A Burg, S Haene, D Perels, P Luethi, N Felber, W Fichtner 2006 IEEE International Symposium on Circuits and Systems, 4 pp., 2006 | 84 | 2006 |
| A real-time 4-stream MIMO-OFDM transceiver: system design, FPGA implementation, and characterization S Haene, D Perels, A Burg IEEE Journal on Selected Areas in Communications 26 (6), 877-889, 2008 | 83 | 2008 |
| A successive cancellation decoder ASIC for a 1024-bit polar code in 180nm CMOS A Mishra, AJ Raymond, LG Amaru, G Sarkis, C Leroux, P Meinerzhagen, ... 2012 IEEE Asian solid state circuits conference (A-SSCC), 205-208, 2012 | 80 | 2012 |
| Computational stereo camera system with programmable control loop S Heinzle, P Greisen, D Gallup, C Chen, D Saner, A Smolic, A Burg, ... ACM Transactions on Graphics (TOG) 30 (4), 94, 2011 | 80 | 2011 |
| VLSI design of approximate message passing for signal restoration and compressive sensing P Maechler, C Studer, DE Bellasi, A Maleki, A Burg, N Felber, H Kaeslin, ... IEEE journal on Emerging and Selected Topics in Circuits and Systems 2 (3 …, 2012 | 79 | 2012 |
| Advanced receiver algorithms for MIMO wireless communications A Burg, M Borgmann, M Wenk, C Studer, H Bölcskei Proceedings of the conference on Design, automation and test in Europe …, 2006 | 77 | 2006 |
| Rapid prototyping for wireless designs: the five-ones approach M Rupp, A Burg, E Beck Signal processing 83 (7), 1427-1444, 2003 | 76 | 2003 |
| A fast and versatile quantum key distribution system with hardware key distillation and wavelength multiplexing N Walenta, A Burg, D Caselunghe, J Constantin, N Gisin, O Guinnard, ... New Journal of Physics 16 (1), 013047, 2014 | 75 | 2014 |
| Efficient ASIC implementation of a real-time depth mapping stereo vision system M Kuhn, S Moser, O Isler, FK Gurkaynak, A Burg, N Felber, H Kaeslin, ... 2003 46th Midwest Symposium on Circuits and Systems 3, 1478-1481, 2003 | 75 | 2003 |
| VLSI circuits for MIMO communication systems AP Burg ETH Zurich, 2006 | 74 | 2006 |
| A low-complexity improved successive cancellation decoder for polar codes O Afisiadis, A Balatsoukas-Stimming, A Burg 2014 48th Asilomar Conference on Signals, Systems and Computers, 2116-2120, 2014 | 72 | 2014 |
Pascal MeinerzhagenStaff Research Scientist, Intel LabsVerified email at intel.com
