| 9.1 A 7nm 4-core AI chip with 25.6 TFLOPS hybrid FP8 training, 102.4 TOPS INT4 inference and workload-aware throttling A Agrawal, SK Lee, J Silberman, M Ziegler, M Kang, S Venkataramani, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 144-146, 2021 | 71 | 2021 |
| RaPiD: AI accelerator for ultra-low precision training and inference S Venkataramani, V Srinivasan, W Wang, S Sen, J Zhang, A Agrawal, ... 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 67 | 2021 |
| Pin accessibility-driven cell layout redesign and placement optimization J Seo, J Jung, S Kim, Y Shin Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 54 | 2017 |
| Routing-free crosstalk prediction R Liang, Z Xie, J Jung, V Chauha, Y Chen, J Hu, H Xiang, GJ Nam Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 36 | 2020 |
| Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags J Jung, Y Nakata, M Yoshimoto, H Kawaguchi International symposium on quality electronic design (ISQED), 216-222, 2013 | 35 | 2013 |
| OpenDesign Flow Database: The infrastructure for VLSI design and design automation research J Jung, IHR Jiang, GJ Nam, VN Kravets, L Behjat, YL Li 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2016 | 17 | 2016 |
| A 7-nm four-core mixed-precision AI chip with 26.2-TFLOPS hybrid-FP8 training, 104.9-TOPS INT4 inference, and workload-aware throttling SK Lee, A Agrawal, J Silberman, M Ziegler, M Kang, S Venkataramani, ... IEEE Journal of Solid-State Circuits 57 (1), 182-197, 2021 | 16 | 2021 |
| Metrics2. 1 and flow tuning in the ieee ceda robust design flow and openroad iccad special session paper J Jung, AB Kahng, S Kim, R Varadarajan 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021 | 16 | 2021 |
| DATC RDF-2019: Towards a complete academic reference design flow J Chen, IHR Jiang, J Jung, AB Kahng, VN Kravets, YL Li, ST Lin, M Woo 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2019 | 14 | 2019 |
| Transient clock power estimation of pre-CTS netlist Y Kwon, J Jung, I Han, Y Shin 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2018 | 14 | 2018 |
| DATC RDF-2020: Strengthening the foundation for academic research in IC physical design J Chen, IHR Jiang, J Jung, AB Kahng, VN Kravets, YL Li, ST Lin, M Woo Proceedings of the 39th International Conference on Computer-Aided Design, 1-6, 2020 | 12 | 2020 |
| DATC RDF: An academic flow from logic synthesis to detailed routing J Jung, IHR Jiang, J Chen, ST Lin, YL Li, VN Kravets, GJ Nam 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-4, 2018 | 12 | 2018 |
| OWARU: Free space-aware timing-driven incremental placement with critical path smoothing J Jung, GJ Nam, LN Reddy, IHR Jiang, Y Shin IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 12 | 2017 |
| DATC RDF: Robust design flow database J Jung, PY Lee, YS Wu, NK Darav, IHR Jiang, VN Kravets, L Behjat, YL Li, ... 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 872-873, 2017 | 12 | 2017 |
| Datc rdf-2021: Design flow and beyond iccad special session paper J Chen, IHR Jiang, J Jung, AB Kahng, S Kim, VN Kravets, YL Li, ... 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-6, 2021 | 10 | 2021 |
| Fault-criticality assessment for AI accelerators using graph convolutional networks A Chaudhuri, J Talukdar, J Jung, GJ Nam, K Chakrabarty 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 9 | 2021 |
| Integrated latch placement and cloning for timing optimization J Jung, GJ Nam, W Chung, Y Shin ACM Transactions on Design Automation of Electronic Systems (TODAES) 24 (2 …, 2019 | 7 | 2019 |
| DATC RDF: An open design flow from logic synthesis to detailed routing J Jung, IHR Jiang, J Chen, ST Lin, YL Li, VN Kravets, GJ Nam arXiv preprint arXiv:1810.01078, 2018 | 7 | 2018 |
| Physical synthesis of DNA circuits with spatially localized gates J Jung, D Hyun, Y Shin 2015 33rd IEEE International Conference on Computer Design (ICCD), 259-265, 2015 | 7 | 2015 |
| FlowTuner: A multi-stage EDA flow tuner exploiting parameter knowledge transfer R Liang, J Jung, H Xiang, L Reddy, A Lvov, J Hu, GJ Nam 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021 | 6 | 2021 |
