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Yvain Thonnart
Yvain Thonnart
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Title
Cited by
Cited by
Year
An asynchronous power aware and adaptive NoC based circuit
E Beigné, F Clermidy, H Lhermet, S Miermont, Y Thonnart, XT Tran, ...
IEEE Journal of solid-state Circuits 44 (4), 1167-1177, 2009
1632009
A fully-asynchronous low-power framework for GALS NoC integration
Y Thonnart, P Vivet, F Clermidy
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
1412010
A 477mW NoC-based digital baseband for MIMO 4G SDR
F Clermidy, C Bernard, R Lemaire, J Martin, I Miro-Panades, Y Thonnart, ...
2010 IEEE International Solid-State Circuits Conference-(ISSCC), 278-279, 2010
1252010
19.2 A 110mK 295µW 28nm FDSOI CMOS quantum integrated circuit with a 2.8 GHz excitation and nA current sensing of an on-chip double quantum dot
L Le Guevel, G Billiot, X Jehl, S De Franceschi, M Zurita, Y Thonnart, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 306-308, 2020
722020
IntAct: A 96-core processor with six chiplets 3D-stacked on an active interposer with distributed interconnects and integrated power management
P Vivet, E Guthmuller, Y Thonnart, G Pillonnet, C Fuguet, I Miro-Panades, ...
IEEE Journal of Solid-State Circuits 56 (1), 79-97, 2020
662020
Design and implementation of a GALS adapter for ANoC based architectures
Y Thonnart, E Beigné, P Vivet
2009 15th IEEE Symposium on Asynchronous Circuits and Systems, 13-22, 2009
662009
An open and reconfigurable platform for 4g telecommunication: Concepts and application
F Clermidy, R Lemaire, X Popon, D Ktenas, Y Thonnart
2009 12th Euromicro conference on digital system design, architectures …, 2009
642009
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm …
P Vivet, E Guthmuller, Y Thonnart, G Pillonnet, G Moritz, I Miro-Panadès, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 46-48, 2020
632020
A 460 mhz at 397 mv, 2.6 ghz at 1.3 v, 32 bits vliw dsp embedding f max tracking
E Beigne, A Valentian, I Miro-Panades, R Wilson, P Flatresse, F Abouzeid, ...
IEEE Journal of Solid-State Circuits 50 (1), 125-136, 2014
602014
A 0.9 pJ/bit, 12.8 GByte/s WideIO memory interface in a 3D-IC NoC-based MPSoC
D Dutoit, C Bernard, S Chéramy, F Clermidy, Y Thonnart, P Vivet, ...
2013 Symposium on VLSI Technology, C22-C23, 2013
592013
A Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links
P Vivet, Y Thonnart, R Lemaire, C Santos, E Beigné, C Bernard, F Darve, ...
IEEE Journal of Solid-State Circuits 52 (1), 33-49, 2016
552016
A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking
R Wilson, E Beigne, P Flatresse, A Valentian, F Abouzeid, T Benoist, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
522014
A pseudo-synchronous implementation flow for WCHB QDI asynchronous circuits
Y Thonnart, E Beigné, P Vivet
2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems …, 2012
502012
Efficiency optimization of silicon photonic links in 65-nm CMOS and 28-nm FDSOI technology nodes
R Polster, Y Thonnart, G Waltener, JL Gonzalez, E Cassan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (12 …, 2016
472016
A 10Gb/s Si-photonic transceiver with 150μW 120μs-lock-time digitally supervised analog microring wavelength stabilization for 1Tb/s/mm2 Die-to-Die Optical …
Y Thonnart, M Zid, JL Gonzalez-Jimenez, G Waltener, R Polster, ...
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 350-352, 2018
432018
Formal verification of CHP specifications with CADP illustration on an asynchronous network-on-chip
G Salaun, W Serwe, Y Thonnart, P Vivet
13th IEEE International Symposium on Asynchronous Circuits and Systems …, 2007
432007
An analytical method for evaluating network-on-chip performance
S Foroutan, Y Thonnart, R Hersemeule, A Jerraya
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
422010
Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs
E Beigné, A Valentian, B Giraud, O Thomas, T Benoist, Y Thonnart, ...
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 613-618, 2013
372013
Asynchronous circuit designs for the Internet of everything: A methodology for ultralow-power circuits with GALS architecture
E Beigne, P Vivet, Y Thonnart, JF Christmann, F Clermidy
IEEE Solid-State Circuits Magazine 8 (4), 39-47, 2016
352016
A Fine-Grain Variation-Aware Dynamic -Hopping AVFS Architecture on a 32 nm GALS MPSoC
I Miro-Panades, E Beigné, Y Thonnart, L Alacoque, P Vivet, S Lesecq, ...
IEEE Journal of Solid-State Circuits 49 (7), 1475-1486, 2014
352014
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