Trong Huynh-Bao
Trong Huynh-Bao
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Vertical GAAFETs for the Ultimate CMOS Scaling
D Yakimets, G Eneman, P Schuddinck, T Huynh Bao, MG Bardon, ...
Electron Devices, IEEE Transactions on 62 (5), 1433-1439, 2015
Vertical device architecture for 5nm and beyond: device & circuit implications
AVY Thean, D Yakimets, TH Bao, P Schuddinck, S Sakhare, MG Bardon, ...
2015 Symposium on VLSI Technology (VLSI Technology), T26-T27, 2015
DTCO at N7 and beyond: patterning and electrical compromises and opportunities
J Ryckaert, P Raghavan, P Schuddinck, T Huynh Bao, A Mallik, ...
SPIE Advanced Lithography, 94270C-94270C-8, 2015
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies
T Huynh Bao, D Yakimets, J Ryckaert, I Ciofi, R Baert, A Veloso, ...
Solid State Device Research Conference (ESSDERC), 2014 44th European, 102-105, 2014
Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells
A Veloso, B Parvais, P Matagne, E Simoen, T Huynh-Bao, V Paraschiv, ...
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs
T Huynh-Bao, S Sakhare, D Yakimets, J Ryckaert, AVY Thean, A Mercha, ...
Transactions on Electron Devices 63 (2), 643-651, 2016
Statistical timing analysis considering device and interconnect variability for BEOL requirements in the 5-nm node and beyond
T Huynh-Bao, J Ryckaert, Z Tőkei, A Mercha, D Verkest, AVY Thean, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (5 …, 2017
Vertical nanowire FET integration and device aspects
A Veloso, E Altamirano-Sánchez, S Brus, BT Chan, M Cupak, M Dehan, ...
ECS Transactions 72 (4), 31, 2016
Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs
T Huynh-Bao, J Ryckaert, S Sakhare, A Mercha, D Verkest, A Thean, ...
Design-Process-Technology Co-optimization for Manufacturability X 9781, 978102, 2016
Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node
S Sakhare, M Perumkunnil, TH Bao, S Rao, W Kim, D Crotti, F Yasin, ...
2018 IEEE International Electron Devices Meeting (IEDM), 18.3. 1-18.3. 4, 2018
Lateral versus vertical gate-all-around FETs for beyond 7nm technologies
D Yakimets, T Huynh Bao, MG Bardon, M Dehan, N Collaert, A Mercha, ...
Device Research Conference (DRC), 2014 72nd Annual, 133-134, 2014
The Complementary FET (CFET) for CMOS scaling beyond N3
J Ryckaert, P Schuddinck, P Weckx, G Bouche, B Vincent, J Smith, ...
2018 IEEE Symposium on VLSI Technology, 141-142, 2018
Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM
T Huynh-Bao, S Sakhare, J Ryckaert, D Yakimets, A Mercha, D Verkest, ...
2015 International Conference on IC Design & Technology (ICICDT), 1-4, 2015
Challenges and opportunities of vertical FET devices using 3D circuit design layouts
A Veloso, T Huynh-Bao, E Rosseel, V Paraschiv, K Devriendt, E Vecchio, ...
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2016
Heterogeneous nano-to wide-scale co-integration of beyond-Si and Si CMOS devices to enhance future electronics
A Thean, N Collaert, IP Radu, N Waldron, C Merckling, L Witters, R Loo, ...
ECS Transactions 66 (4), 3, 2015
Vertical Nanowire and Nanosheet FETs: Device Features, Novel Schemes for Improved Process Control and Enhanced Mobility, Potential for Faster & More Energy Efficient Circuits
A Veloso, G Eneman, T Huynh-Bao, A Chasin, E Simoen, E Vecchio, ...
2019 IEEE International Electron Devices Meeting (IEDM), 11.1. 1-11.1. 4, 2019
Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems
M Komalan, S Sakhare, TH Bao, S Rao, W Kim, C Tenllado, JI Gómez, ...
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
Challenges on surface conditioning in 3D device architectures: triple-gate FinFETs, gate-all-around lateral and vertical nanowire FETs
A Veloso, V Paraschiv, E Vecchio, K Devriendt, W Li, E Simoen, BT Chan, ...
ECS Transactions 80 (2), 3, 2017
ECS Meeting Abstracts
EY Lee
MA2009-02 3213, 2009
SRAM designs for 5nm node and beyond: Opportunities and challenges
T Huynh-Bao, S Sakhare, J Ryckaert, A Spessot, D Verkest, A Mocuta
2017 IEEE International Conference on IC Design and Technology (ICICDT), 1-4, 2017
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