Shmuel Wimer
Shmuel Wimer
Professor Emeritus of Computer Engineering, Bar-Ilan University
Verified email at biu.ac.il - Homepage
Title
Cited by
Cited by
Year
Arrangements for automatic re-legging of transistors
S Wimer
US Patent 7,079,989, 2006
1942006
Optimal chaining of CMOS transistors in a functional cell
S Wimer, RY Pinter, JA Feldman
IEEE transactions on computer-aided design of integrated circuits and …, 1987
1341987
Optimal aspect ratios of building blocks in VLSI
S Wimer, I Koren, I Cederbaum
IEEE transactions on computer-aided design of integrated circuits and …, 1989
1071989
Floorplans, planar graphs, and layouts
S Wimer, I Koren, I Cederbaum
IEEE Transactions on Circuits and Systems 35 (3), 267-278, 1988
871988
The optimal fan-out of clock network for power minimization by adaptive gating
S Wimer, I Koren
IEEE Transactions on very large scale integration (VLSI) systems 20 (10 …, 2011
752011
Design flow for flip-flop grouping in data-driven clock gating
S Wimer, I Koren
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (4), 771-778, 2013
722013
Depth-first-search and dynamic programming algorithms for efficient CMOS cell generation
R Bar-Yehuda, JA Feldman, RY Pinter, S Wimer
IEEE transactions on computer-aided design of integrated circuits and …, 1989
481989
The Wiener maximum quadratic assignment problem
E Cela, NS Schmuck, S Wimer, GJ Woeginger
Discrete Optimization 8 (3), 411-416, 2011
392011
A cost effective centralized adaptive routing for networks-on-chip
R Manevich, I Cidon, A Kolodny, S Wimer
2011 14th Euromicro Conference on Digital System Design, 39-46, 2011
362011
Timing-aware power-optimal ordering of signals
K Moiseev, A Kolodny, S Wimer
ACM Transactions on Design Automation of Electronic Systems (TODAES) 13 (4 …, 2008
272008
Analysis of strategies for constructive general block placement
S Wimer, I Koren
IEEE transactions on computer-aided design of integrated circuits and …, 1988
261988
Optimal bus sizing in migration of processor design
S Wimer, S Michaely, K Moiseev, A Kolodny
IEEE Transactions on Circuits and Systems I: Regular Papers 53 (5), 1089-1100, 2006
192006
A look-ahead clock gating based on auto-gated flip-flops
S Wimer, A Albahari
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (5), 1465-1472, 2014
182014
System and method for generating a clock gating network for logic circuits
S Wimer
US Patent App. 13/361,986, 2013
172013
Power-delay optimization in VLSI microprocessors by wire spacing
K Moiseev, A Kolodny, S Wimer
ACM Transactions on Design Automation of Electronic Systems (TODAES) 14 (4 …, 2009
172009
On optimal flip-flop grouping for VLSI power minimization
S Wimer
Operations Research Letters 41 (5), 486-489, 2013
142013
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing
K Moiseev, S Wimer, A Kolodny
2006 IEEE International Symposium on Circuits and Systems, 4 pp., 2006
142006
On optimal ordering of signals in parallel wire bundles
K Moiseev, S Wimer, A Kolodny
Integration 41 (2), 253-268, 2008
122008
Mixing drivers in clock-tree for power supply noise reduction
Y Kaplan, S Wimer
IEEE Transactions on Circuits and Systems I: Regular Papers 62 (5), 1382-1391, 2015
102015
Multi-Net Optimization of VLSI Interconnect
K Moiseev, A Kolodny, S Wimer
Springer New York, 2015
102015
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