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Dogan Ulus
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Timed pattern matching
D Ulus, T Ferrère, E Asarin, O Maler
International Conference on Formal Modeling and Analysis of Timed Systems …, 2014
632014
First-order temporal logic monitoring with BDDs
K Havelund, D Peled, D Ulus
Formal Methods in System Design 56 (1), 1-21, 2020
612020
Online timed pattern matching using derivatives
D Ulus, T Ferrère, E Asarin, O Maler
International Conference on Tools and Algorithms for the Construction and …, 2016
482016
AMT 2.0: qualitative and quantitative trace analysis with extended signal temporal logic
D Ničković, O Lebeltel, O Maler, T Ferrère, D Ulus
International Journal on Software Tools for Technology Transfer 22 (6), 741-758, 2020
422020
Montre: A Tool for Monitoring Timed Regular Expressions
D Ulus
International Conference on Computer Aided Verification, 329-335, 2017
402017
On the quantitative semantics of regular expressions over real-valued signals
A Bakhirkin, T Ferrère, O Maler, D Ulus
International Conference on Formal Modeling and Analysis of Timed Systems …, 2017
272017
Measuring with timed patterns
T Ferrère, O Maler, D Ničković, D Ulus
International Conference on Computer Aided Verification, 322-337, 2015
242015
Dejavu: A monitoring tool for first-order temporal logic
K Havelund, D Peled, D Ulus
2018 IEEE Workshop on Monitoring and Testing of Cyber-Physical Systems (MT …, 2018
132018
Derivatives of quantitative regular expressions
R Alur, K Mamouras, D Ulus
Models, algorithms, logics and tools, 75-95, 2017
122017
Special session: Embedded software for robotics: Challenges and future directions
H Abbas, I Saha, Y Shoukry, R Ehlers, G Fainekos, R Gupta, R Majumdar, ...
2018 International Conference on Embedded Software (EMSOFT), 1-10, 2018
11*2018
First-order Temporal Logic Monitoring with BDDs, FMCAD’17
K Havelund, D Peled, D Ulus
IEEE, 2017
102017
Timescales: A benchmark generator for MTL monitoring tools
D Ulus
International Conference on Runtime Verification, 402-412, 2019
92019
Specifying timed patterns using temporal logic
D Ulus, O Maler
Proceedings of the 21st International Conference on Hybrid Systems …, 2018
92018
Online monitoring of metric temporal logic using sequential networks
D Ulus
arXiv preprint arXiv:1901.00175, 2019
72019
Reactive control meets runtime verification: A case study of navigation
D Ulus, C Belta
International Conference on Runtime Verification, 368-374, 2019
62019
Using haloes in mixed-signal assertion based verification
D Ulus, A Sen
2012 IEEE International High Level Design Validation and Test Workshop …, 2012
62012
Sequential circuits from regular expressions revisited
D Ulus
arXiv preprint arXiv:1801.08979, 2018
52018
Combining the temporal and epistemic dimensions for MTL monitoring
E Asarin, O Maler, D Nickovic, D Ulus
International Conference on Formal Modeling and Analysis of Timed Systems …, 2017
52017
Pattern Matching with Time: Theory and Applications
D Ulus
Universite Grenoble-Alpes (UGA), 2018
32018
Analog layer extensions for analog/mixed-signal assertion languages
D Ulus, A Sen, F Baskaya
2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration …, 2013
12013
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