| Semiconductor devices with varying threshold voltage and fabrication methods thereof B Kannan, U Kwon, S Krishnan, T Ando, V Narayanan US Patent 9,748,145, 2017 | 375 | 2017 |
| Enabling enhanced reliability and mobility for replacement gate planar and finfet structures T Ando, EA Cartier, K Choi, WL Lai, V Narayanan, R Ramachandran US Patent App. 14/696,015, 2015 | 301 | 2015 |
| FinFET parasitic capacitance reduction using air gap T Ando, JB Chang, SK Kanakasabapathy, P Kulkarni, TE Standaert, ... US Patent 8,637,384, 2014 | 278 | 2014 |
| Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging? T Ando Materials 5 (3), 478-500, 2012 | 202 | 2012 |
| A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications S Krishnan, U Kwon, N Moumen, MW Stoker, ECT Harley, S Bedell, ... 2011 International Electron Devices Meeting, 28.1. 1-28.1. 4, 2011 | 129 | 2011 |
| Understanding mobility mechanisms in extremely scaled HfO2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and Vt-tuning dipoles with gate-first process T Ando, MM Frank, K Choi, C Choi, J Bruley, M Hopstaken, M Copel, ... Electron Devices Meeting (IEDM), 2009 IEEE International, 1-4, 2009 | 122 | 2009 |
| Fundamental aspects of HfO2-based high-k metal gate stack reliability and implications on tinv-scaling E Cartier, A Kerber, T Ando, MM Frank, K Choi, S Krishnan, B Linder, ... 2011 International Electron Devices Meeting, 18.4. 1-18.4. 4, 2011 | 121 | 2011 |
| High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing M Chudzik, B Doris, R Mo, J Sleight, E Cartier, C Dewan, D Park, H Bu, ... VLSI Technology, 2007 IEEE Symposium on, 194-195, 2007 | 119 | 2007 |
| FinFET parasitic capacitance reduction using air gap T Ando, JB Chang, SK Kanakasabapathy, P Kulkarni, TE Standaert, ... US Patent 8,637,930, 2014 | 117 | 2014 |
| Solid-state imaging device, method for producing same, and camera Y Maruyama, T Yamaguchi, T Ando, S Hiyama, Y Ohgishi US Patent App. 11/677,645, 2007 | 114 | 2007 |
| Signal and noise extraction from analog memory elements for neuromorphic computing N Gong, T Idé, S Kim, I Boybat, A Sebastian, V Narayanan, T Ando Nature communications 9 (1), 2102, 2018 | 107 | 2018 |
| 22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL S Narasimha, P Chang, C Ortolland, D Fried, E Engbrecht, K Nummy, ... 2012 International Electron Devices Meeting, 3.3. 1-3.3. 4, 2012 | 103 | 2012 |
| Physical origins of mobility degradation in extremely scaled SiO2/HfO2 gate stacks with La and Al induced dipoles T Ando, M Copel, J Bruley, MM Frank, H Watanabe, V Narayanan Applied Physics Letters 96 (13), 132904-132904-3, 2010 | 85 | 2010 |
| Scavenging metal stack for a high-k gate dielectric T Ando, C Choi, MM Frank, V Narayanan US Patent 7,989,902, 2011 | 63 | 2011 |
| Metal-oxide based, CMOS-compatible ECRAM for deep learning accelerator S Kim, T Todorov, M Onen, T Gokmen, D Bishop, P Solomon, KT Lee, ... 2019 IEEE International Electron Devices Meeting (IEDM), 35.7. 1-35.7. 4, 2019 | 62 | 2019 |
| Extremely scaled gate-first high-k/metal gate stack with EOT of 0.55 nm using novel interfacial layer scavenging techniques for 22nm technology node and beyond K Choi, H Jagannathan, C Choi, L Edge, T Ando, M Frank, P Jamison, ... VLSI Technology, 2009 Symposium on, 138-139, 2009 | 59 | 2009 |
| High-k metal gate fundamental learning and multi-Vt options for stacked nanosheet gate-all-around transistor J Zhang, T Ando, CW Yeung, M Wang, O Kwon, R Galatage, R Chao, ... 2017 IEEE International Electron Devices Meeting (IEDM), 22.1. 1-22.1. 4, 2017 | 58 | 2017 |
| Method for fabricating semiconductor device W Wang, T Ando, Y Hikosaka US Patent 7,390,678, 2008 | 56* | 2008 |
| Enabling enhanced reliability and mobility for replacement gate planar and FinFET structures T Ando, EA Cartier, K Choi, WL Lai, V Narayanan, R Ramachandran US Patent 9,099,393, 2015 | 54 | 2015 |
| Inversion thickness reduction in high-k gate stacks formed by replacement gate processes T Ando, V Narayanan US Patent App. 13/100,371, 2012 | 51 | 2012 |
Pouya HashemiIBM Manager and Senior Research ScientistVerified email at us.ibm.com
