A low-latency and low-complexity point-multiplication in ECC R Salarifard, S Bayat-Sarmadi, H Mosanaei-Boorani
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (9), 2869-2877, 2018
49 2018 An efficient low-latency point-multiplication over curve25519 R Salarifard, S Bayat-Sarmadi
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (10), 3854-3862, 2019
30 2019 Low-latency Keccak at any arbitrary order S Zarei, AR Shahmirzadi, H Soleimany, R Salarifard, A Moradi
IACR Transactions on Cryptographic Hardware and Embedded Systems, 388-411, 2021
14 2021 High-Throughput Low-Complexity Unified Multipliers Over in Dual and Triangular Bases R Salarifard, S Bayat-Sarmadi, M Farmani
IEEE Transactions on Circuits and Systems I: Regular Papers 63 (11), 1944-1953, 2016
6 2016 Efficient accelerator for NTT-based polynomial multiplication R Salarifard, H Soleimany
Cryptology ePrint Archive, 2023
2 2023 A robust SIFT-based descriptor for video classification R Salarifard, MA Hosseini, M Karimian, S Kasaei
Seventh International Conference on Machine Vision (ICMV 2014) 9445, 278-282, 2015
1 2015 FPGA Implementation of Polynomial Multiplication in NTRU Prime PQC Algorithms R Rashidian, R Salarifard, A Jahanian
Biannual Journal Monadi for Cyberspace Security (AFTA) 12 (2), 73-80, 2024
2024 Efficient NTT Multiplier of NTRU Prime PQC Algorithm R Salarifard, R Rashidian, R Kharazmi, A Jahanian
Journal of Innovations in Computer Science and Engineering (JICSE) 1 (1), 69-75, 2023
2023 A High-Speed Systolic Field Multiplication for Edwards 25519 Curve MR Akhoundi Zardeyni, R Salarifard
Biannual Journal Monadi for Cyberspace Security (AFTA) 11 (1), 67-74, 2022
2022 ISeCure M Hajisoltani, R Salarifard, H Soleimany
2022 Secure and Low-Area Implementation of the AES Using FPGA M Hajisoltani, R Salarifard, H Soleimany
THE ISC INTERNATIONAL JOURNAL OF INFORMATION SECURITY 14 (3), 93-99, 2022
2022 Lightweight and Efficient Implementation of AES R Salarifard