Ramiro Taco
Ramiro Taco
Verified email at dimes.unical.it
Title
Cited by
Cited by
Year
Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI
R Taco, I Levi, M Lanuzza, A Fish
Solid-State Electronics 117, 185-192, 2016
282016
Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design
R Taco, I Levi, A Fish, M Lanuzza
2014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel …, 2014
132014
Gate‐level body biasing for subthreshold logic circuits: analytical modeling and design guidelines
D Albano, M Lanuzza, R Taco, F Crupi
International Journal of Circuit Theory and Applications 43 (11), 1523-1540, 2015
102015
Dynamic gate-level body biasing for subthreshold digital design
M Lanuzza, R Taco, D Albano
2014 IEEE 5th Latin American Symposium on Circuits and Systems, 1-4, 2014
102014
Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology
R Taco, I Levi, M Lanuzza, A Fish
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 41-44, 2016
62016
Ultra-low-voltage self-body biasing scheme and its application to basic arithmetic circuits
R Taco, M Lanuzza, D Albano
VLSI Design 2015, 2015
62015
Evaluation of Dual Mode Logic in 28nm FD-SOI technology
R Taco, I Levi, M Lanuzza, A Fish
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
42017
An 88-fJ/40-MHz [0.4 V]–0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI
R Taco, I Levi, M Lanuzza, A Fish
IEEE Journal of Solid-State Circuits 54 (2), 560-568, 2018
32018
Low voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI
R Taco, I Levi, M Lanuzza, A Fish
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2015
32015
Improving speed and power characteristics of pulse-triggered flip-flops
M Lanuzza, R Taco
2014 IEEE 5th Latin American Symposium on Circuits and Systems, 1-4, 2014
22014
Live Demo: An 88fJ/40 MHz [0.4 V]–0.61 pJ/1GHz [0.9 V] Dual Mode Logic 8× 8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI
R Taco, I Levi, M Lanuzza, A Fish
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-1, 2019
2019
Efficiency of Dual Mode Logic in Nanoscale Technology Nodes
N Shavit, R Taco, A Fish
2018 IEEE International Conference on the Science of Electrical Engineering …, 2018
2018
Process Variation-Aware Datapath Employing Dual Mode Logic
N Shavit, I Stanger, R Taco, A Fish
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018
2018
Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI
R Taco, I Levi, M Lanuzza, A Fish
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2017
2017
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