Volgen
Chandu Visweswariah
Chandu Visweswariah
Utopus Insights
Geverifieerd e-mailadres voor utopusinsights.com
Titel
Geciteerd door
Geciteerd door
Jaar
First-order incremental block-based statistical timing analysis
C Visweswariah, K Ravindran, K Kalafala, SG Walker, S Narayan
Proceedings of the 41st annual Design Automation Conference, 331-336, 2004
9802004
Electronic Circuit & System Simulation Methods (SRE)
L Pillage
McGraw-Hill, Inc., 1998
5911998
Death, taxes and failing chips
C Visweswariah
Proceedings of the 40th annual Design Automation Conference, 343-347, 2003
2872003
Method, system, and program product for computing a yield gradient from statistical timing
C Visweswariah, JJ Xiong, V Zolotov
US Patent 7,480,880, 2009
2702009
Parameterized block-based statistical timing analysis with non-Gaussian parameters, nonlinear delay functions
H Chang, V Zolotov, S Narayan, C Visweswariah
Proceedings of the 42nd Annual Design Automation Conference, 71-76, 2005
2552005
Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices
PM Williams, EK Cho, DJ Hathaway, MT Hsu, LK Lange, GA Northrop, ...
US Patent 7,093,208, 2006
2452006
Statistical timing for parametric yield prediction of digital integrated circuits
JAG Jess, K Kalafala, SR Naidu, RHJM Otten, C Visweswariah
Proceedings of the 40th annual Design Automation Conference, 932-937, 2003
2122003
Uncertainty-aware circuit optimization
X Bai, C Visweswariah, PN Strenski
Proceedings of the 39th annual Design Automation Conference, 58-63, 2002
1342002
Piecewise approximate circuit simulation
C Visweswariah, RA Rohrer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1991
1291991
Gradient-based optimization of custom circuits using a static-timing formulation
AR Conn, IM Elfadel, WW Molzen Jr, PR O'brien, PN Strenski, ...
Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 452-459, 1999
1281999
Optimization of custom MOS circuits by transistor sizing
AR Conn, PK Coulman, RA Haring, GL Morrill, C Visweswariah
The Best of ICCAD: 20 Years of Excellence in Computer-Aided Design, 347-364, 2003
932003
JiffyTune: Circuit optimization using time-domain sensitivities
AR Conn, PK Coulman, RA Haring, GL Morrill, C Visweswariah, CW Wu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1998
921998
Statistical path selection for at-speed test
V Zolotov, J Xiong, H Fatemi, C Visweswariah
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
892010
System and method for incremental statistical timing analysis of digital circuits
C Visweswariah
US Patent 7,111,260, 2006
812006
System and method for statistical timing analysis of digital circuits
C Visweswariah
US Patent 7,428,716, 2008
792008
System and method for correlated process pessimism removal for static timing analysis
K Kalafala, P Qi, DJ Hathaway, AJ Suess, C Visweswariah
US Patent 7,117,466, 2006
742006
Criticality computation in parameterized statistical timing
J Xiong, V Zolotov, N Venkateswaran, C Visweswariah
Proceedings of the 43rd annual Design Automation Conference, 63-68, 2006
732006
System and method for statistical modeling and statistical timing analysis of integrated circuits
J Jess, C Visweswariah
US Patent App. 10/184,329, 2004
582004
Noise considerations in circuit optimization
AR Conn, RA Haring, C Visweswariah
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided …, 1998
581998
Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation
C Visweswariah, AR Conn
1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of …, 1999
541999
Het systeem kan de bewerking nu niet uitvoeren. Probeer het later opnieuw.
Artikelen 1–20