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Valeriya Kilchytska
Valeriya Kilchytska
Geverifieerd e-mailadres voor uclouvain.be
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INFLUENCE OF DEVICE ENGINEERING ON THE ANALOG AND RF PERFORMANCES OF SOI MOSFETS
V Kilchytska, A Neve, L Vancaillie, D Levacq, S Adriaensen, H van Meer, ...
Emerging nanoelectronics: life with and after CMOS 1, 375, 2005
2662005
Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization
JP Raskin, TM Chung, V Kilchytska, D Lederer, D Flandre
IEEE Transactions on Electron Devices 53 (5), 1088-1095, 2006
1372006
FinFET analogue characterization from DC to 110 GHz
D Lederer, V Kilchytska, T Rudenko, N Collaert, D Flandre, A Dixit, ...
Solid-State Electronics 49 (9), 1488-1496, 2005
1262005
Gm/Id Method for Threshold Voltage Extraction Applicable in Advanced MOSFETs With Nonlinear Behavior Above Threshold
D Flandre, V Kilchytska, T Rudenko
Electron Device Letters, IEEE 31 (9), 930-932, 2010
972010
Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications
O Moldovan, A Cerdeira, D Jiménez, JP Raskin, V Kilchytska, D Flandre, ...
Solid-state electronics 51 (5), 655-661, 2007
762007
A 3-D analytical physically based model for the subthreshold swing in undoped trigate FinFETs
H Abd El Hamid, JR Guitart, V Kilchytska, D Flandre, B Iñiguez
IEEE transactions on electron devices 54 (9), 2487-2496, 2007
752007
Effective mobility in FinFET structures with HfO2 and SiON gate dielectrics and TaN gate electrode
T Rudenko, N Collaert, S De Gendt, V Kilchytska, M Jurczak, D Flandre
Microelectronic Engineering 80, 386-389, 2005
712005
Perspective of FinFETs for analog applications
V Kilchytska, N Collaert, R Rooyackers, D Lederer, JP Raskin, D Flandre
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat …, 2004
692004
UTBB SOI MOSFETs analog figures of merit: Effects of ground plane and asymmetric double-gate regime
MKM Arshad, S Makovejev, S Olsen, F Andrieu, JP Raskin, D Flandre, ...
Solid-state electronics 90, 56-64, 2013
682013
On the MOSFET threshold voltage extraction by transconductance and transconductance-to-current ratio change methods: Part II—Effect of drain voltage
T Rudenko, V Kilchytska, MKM Arshad, JP Raskin, A Nazarov, D Flandre
IEEE Transactions on Electron Devices 58 (12), 4180-4188, 2011
642011
On the MOSFET threshold voltage extraction by transconductance and transconductance-to-current ratio change methods: Part I—Effect of gate-voltage-dependent mobility
T Rudenko, V Kilchytska, MKM Arshad, JP Raskin, A Nazarov, D Flandre
IEEE Transactions on Electron Devices 58 (12), 4172-4179, 2011
602011
Wide frequency band assessment of 28 nm FDSOI technology platform for analogue and RF applications
S Makovejev, BK Esfeh, V Barral, N Planes, M Haond, D Flandre, ...
Solid-State Electronics 108, 47-52, 2015
592015
Time and frequency domain characterization of transistor self-heating
S Makovejev, SH Olsen, V Kilchytska, JP Raskin
IEEE transactions on electron devices 60 (6), 1844-1851, 2013
552013
Impact of self-heating and substrate effects on small-signal output conductance in UTBB SOI MOSFETs
S Makovejev, JP Raskin, MKM Arshad, D Flandre, S Olsen, F Andrieu, ...
Solid-State Electronics 71, 93-100, 2012
542012
Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel
S Burignat, D Flandre, MKM Arshad, V Kilchytska, F Andrieu, O Faynot, ...
Solid-state electronics 54 (2), 213-219, 2010
542010
Floating effective back-gate effect on the small-signal output conductance of SOI MOSFETs
V Kilchytska, D Levacq, D Lederer, JP Raskin, D Flandre
IEEE Electron Device Letters 24 (6), 414-416, 2003
542003
Ultra-thin body and thin-BOX SOI CMOS technology analog figures of merit
V Kilchytska, MKM Arshad, S Makovejev, S Olsen, F Andrieu, T Poiroux, ...
Solid-State Electronics 70, 50-58, 2012
522012
Assessment of 28 nm UTBB FD-SOI technology platform for RF applications: Figures of merit and effect of parasitic elements
BK Esfeh, V Kilchytska, V Barral, N Planes, M Haond, D Flandre, ...
Solid-State Electronics 117, 130-137, 2016
512016
Carrier mobility in undoped triple-gate FinFET structures and limitations of its description in terms of top and sidewall channel mobilities
T Rudenko, V Kilchytska, N Collaert, M Jurczak, A Nazarov, D Flandre
IEEE transactions on electron devices 55 (12), 3532-3541, 2008
502008
Experimental study of transconductance and mobility behaviors in ultra-thin SOI MOSFETs with standard and thin buried oxides
T Rudenko, V Kilchytska, S Burignat, JP Raskin, F Andrieu, O Faynot, ...
Solid-State Electronics 54 (2), 164-170, 2010
472010
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