Ashish Verma Penumatcha
Ashish Verma Penumatcha
Components Research, Intel Corp.
Verified email at - Homepage
Cited by
Cited by
High Performance Multilayer MoS2 Transistors with Scandium Contacts
S Das, HY Chen, AV Penumatcha, J Appenzeller
Nano letters 13 (1), 100-105, 2013
Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model
AV Penumatcha, RB Salazar, J Appenzeller
Nature communications 6 (1), 1-9, 2015
Strain engineering for transition metal dichalcogenides based field effect transistors
T Shen, AV Penumatcha, J Appenzeller
ACS nano 10 (4), 4712-4718, 2016
Spin transfer torque in a graphene lateral spin valve assisted by an external magnetic field
CC Lin, AV Penumatcha, Y Gao, VQ Diep, J Appenzeller, Z Chen
Nano letters 13 (11), 5177-5181, 2013
The Origins and Characteristics of the Threshold Voltage Variability of Quasi-Ballistic Single-Walled Carbon Nanotube Field-Effect Transistors
Q Cao, SJ Han, AV Penumatcha, MM Frank, GS Tulevski, J Tersoff, ...
ACS nano, 2015
Limitations of the High-Low C-V Technique for MOS Interfaces With Large Time Constant Dispersion
AV Penumatcha, S Swandono, JA Cooper
IEEE transactions on electron devices 60 (3), 923-926, 2013
Improvement of spin transfer torque in asymmetric graphene devices
CC Lin, Y Gao, AV Penumatcha, VQ Diep, J Appenzeller, Z Chen
ACS nano 8 (4), 3807-3812, 2014
Scaling of device variability and subthreshold swing in ballistic carbon nanotube transistors
Q Cao, J Tersoff, SJ Han, AV Penumatcha
Physical Review Applied 4 (2), 024022, 2015
Spin-orbit torque based magnetization switching in Pt/Cu/[Co/Ni]5 multilayer structures
V Ostwal, A Penumatcha, YM Hung, AD Kent, J Appenzeller
Journal of Applied Physics 122 (21), 213905, 2017
Spin-torque switching of a nano-magnet using giant spin hall effect
AV Penumatcha, SR Das, Z Chen, J Appenzeller
AIP Advances 5 (10), 107144, 2015
Impact of scaling on the dipolar coupling in magnet–insulator–magnet structures
AV Penumatcha, CC Lin, VQ Diep, S Datta, J Appenzeller, Z Chen
IEEE Transactions on Magnetics 52 (1), 1-7, 2015
Electrical evidence of disorder at the SiO2/4H-SiC MOS interface and its effect on electron transport
S Swandono, A Penumatcha, JA Cooper
70th Device Research Conference, 167-168, 2012
Transistor device with variously conformal gate dielectric layers
SH Sung, J Kavalieros, I Young, M Metz, U Avci, D Merrill, ...
US Patent App. 16/363,632, 2020
Piezo-resistive transistor based resonator with anti-ferroelectric gate dielectric
T Gosavi, CC Lin, R Kim, AV Penumatcha, U Avci, I Young
US Patent App. 16/238,419, 2020
Advancing Monolayer 2D NMOS and PMOS Transistor Integration From Growth to van der Waals Interface Engineering for Ultimate CMOS Scaling
CJ Dorow, KP O’Brien, CH Naylor, S Lee, A Penumatcha, A Hsiao, ...
2021 Symposium on VLSI Technology, 1-2, 2021
Multilayer high-k gate dielectric for a high performance logic transistor
SH Sung, AV Penumatcha, SC Chang, D Merrill, IC Tung, N Haratipour, ...
US Patent App. 16/700,757, 2021
Fefet with embedded conductive sidewall spacers and process for forming the same
S Shivaraman, SH Sung, AV Penumatcha, UE Avci
US Patent App. 16/700,782, 2021
3d-ferroelectric random access memory (3d-fram)
S Shivaraman, SC Chang, AV Penumatcha, N Haratipour, UE Avci
US Patent App. 16/599,422, 2021
Integrated circuit device with a two-dimensional semiconductor material and a dielectric material that includes fixed charges
AV Penumatcha, U Avci, I Young
US Patent 10,886,265, 2021
Vertical memory control circuitry located in interconnect layers
AV Penumatcha, DH Morris, UE Avci, IA Young
US Patent 10,886,286, 2021
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