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Ashis Kumar Mal
Ashis Kumar Mal
Professor of ECE, NIT Durgapur
Geverifieerd e-mailadres voor ece.nitdgp.ac.in - Homepage
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Direct correlation between mechanical failure and metallurgical reaction in flip chip solder joints
CY Liu, C Chen, AK Mal, KN Tu
Journal of Applied Physics 85 (7), 3882-3886, 1999
981999
A low voltage high output impedance bulk driven regulated cascode current mirror
N Lakkamraju, AK Mal
2011 3rd International Conference on Electronics Computer Technology 3, 79-83, 2011
172011
On-chip antennas using standard CMOS technology: A brief overview
S Mandal, SK Mandal, AK Mal
2017 International Conference on Innovations in Electronics, Signal …, 2017
162017
Uncoercibility in e-voting and eauctioning mechanisms using deniable encryption
J Howlader, V Nair, S Basu, AK Mal
International Journal of Network Security and Its Applications 3 (2), 97-109, 2011
162011
Design of tunable folded cascode differential amplifier using pdm
AK Mal, R Todani, OP Hari
2011 IEEE Symposium on Computers & Informatics, 296-301, 2011
152011
A miniaturized CPW-fed on-chip UWB monopole antenna with band-notch characteristics
S Mandal, A Karmakar, H Singh, SK Mandal, R Mahapatra, AK Mal
International Journal of Microwave and Wireless Technologies 12 (1), 95-102, 2020
142020
Non Overlapping Clock (NOC) generator for low frequency switched capacitor circuits
AK Mal, R Todani
IEEE Technology Students' Symposium, 226-231, 2011
132011
Symbiotic organisms search algorithm for optimal design of CMOS two‐stage op‐amp with nulling resistor and robust bias circuit
S Ghosh, B Prasad De, R Kar, AK Mal
IET Circuits, Devices & Systems 13 (5), 679-688, 2019
122019
Performance enhancement of a VCO using symbolic modelling and optimisation
M Panda, SK Patnaik, AK Mal
IET Circuits, Devices & Systems 12 (2), 196-202, 2018
122018
A high speed counter for analog-to-digital converters
PR Thota, AK Mal
2016 International Conference on Microelectronics, Computing and …, 2016
122016
Sampled analog architecture for DCT and DST
AK Mal, A Basu, AS Dhar
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No …, 2004
122004
Digital controlled analog architecture for DCT and DST using capacitor switching
A Basu, AK Mal, AS Dhar
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No …, 2004
112004
Analog sampled data architecture for discrete Hartley transform
AK Mal, AS Dhar
TENCON 2003. Conference on Convergent Technologies for Asia-Pacific Region 3 …, 2003
112003
Design of low noise amplifier for sensor applications
D Jana, AK Mal
2017 Devices for Integrated Circuit (DevIC), 451-455, 2017
102017
Sealed‐bid auction: a cryptographic solution to bid‐rigging attack in the collusive environment
J Howlader, AK Mal
Security and Communication Networks 8 (18), 3415-3440, 2015
102015
Practical receipt-free sealed-bid auction in the coercive environment
J Howlader, SK Roy, AK Mal
Information Security and Cryptology--ICISC 2013: 16th International …, 2014
102014
Simplified design method for fully differential gain-boosted folded cascade OTA
NN Ghosh, R Todani, C Chaudhuri, AK Mal
2013 IEEE Conference on Information & Communication Technologies, 943-948, 2013
102013
Impact of burst assembly algorithms on data loss in OBS networks under time-correlated traffic input
S Choudhury, G Chakraborty, A Mal
Journal of Optical Communications and Networking 2 (12), 1063-1076, 2010
102010
An explicit approach for bandwidth evaluation of on-chip VLSI RC interconnects with current mode signaling technique
R Kar, KR Reddy, AK Mal, AK Bhattacharjee
2010 Second International conference on Computing, Communication and …, 2010
10*2010
Delay analysis for on-chip VLSI interconnect using gamma distribution function
R Kar, V Maheshwari, AK Mal, AK Bhattacharjee
International Journal of Computer Application 1 (3), 65-68, 2010
102010
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Artikelen 1–20