Ashis Kumar Mal
Ashis Kumar Mal
Professor of ECE, NIT Durgapur
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Geciteerd door
Geciteerd door
Direct correlation between mechanical failure and metallurgical reaction in flip chip solder joints
CY Liu, C Chen, AK Mal, KN Tu
Journal of Applied Physics 85 (7), 3882-3886, 1999
A low voltage high output impedance bulk driven regulated cascode current mirror
N Lakkamraju, AK Mal
2011 3rd International Conference on Electronics Computer Technology 3, 79-83, 2011
Design of tunable folded cascode differential amplifier using pdm
AK Mal, R Todani, OP Hari
2011 IEEE Symposium on Computers & Informatics, 296-301, 2011
Sampled analog architecture for DCT and DST
AK Mal, A Basu, AS Dhar
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No …, 2004
Digital controlled analog architecture for DCT and DST using capacitor switching
A Basu, AK Mal, AS Dhar
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No …, 2004
Analog sampled data architecture for discrete Hartley transform
AK Mal, AS Dhar
TENCON 2003. Conference on Convergent Technologies for Asia-Pacific Region 3 …, 2003
Uncoercibility in e-voting and eauctioning mechanisms using deniable encryption
J Howlader, V Nair, S Basu, AK Mal
International Journal of Network Security and Its Applications 3 (2), 97-109, 2011
An explicit approach for bandwidth evaluation of on-chip VLSI RC interconnects with current mode signaling technique
R Kar, KR Reddy, AK Mal, AK Bhattacharjee
2010 Second International conference on Computing, Communication and …, 2010
Delay analysis for on-chip vlsi interconnect using gamma distribution function
R Kar, V Maheshwari, AK Mal, AK Bhattacharjee
International Journal of Computer Applications 975, 8887, 2010
A miniaturized CPW-fed on-chip UWB monopole antenna with band-notch characteristics
S Mandal, A Karmakar, H Singh, SK Mandal, R Mahapatra, AK Mal
International Journal of Microwave and Wireless Technologies 12 (1), 95-102, 2020
Sealed‐bid auction: a cryptographic solution to bid‐rigging attack in the collusive environment
J Howlader, AK Mal
Security and Communication Networks 8 (18), 3415-3440, 2015
Non Overlapping Clock (NOC) generator for low frequency switched capacitor circuits
AK Mal, R Todani
IEEE Technology Students' Symposium, 226-231, 2011
Impact of burst assembly algorithms on data loss in OBS networks under time-correlated traffic input
S Choudhury, G Chakraborty, AK Mal
Journal of Optical Communications and Networking 2 (12), 1063-1076, 2010
On-chip antennas using standard CMOS technology: A brief overview
S Mandal, SK Mandal, AK Mal
2017 International Conference on Innovations in Electronics, Signal …, 2017
Simplified design method for fully differential gain-boosted folded cascade OTA
NN Ghosh, R Todani, C Chaudhuri, AK Mal
2013 IEEE Conference on Information & Communication Technologies, 943-948, 2013
Simulator based device sizing technique for operational amplifiers
R Todani, AK Mal
WSEAS Trans. Circ. Syst 13 (1), 11-28, 2014
An explicit approach for delay evaluation for on-chip RC interconnects using beta distribution function by moment matching technique
R Kar, V Maheshwari, S Pathak, MSK Reddy, AK Mal, AK Bhattacharjee
2010 International Conference on Recent Trends in Information …, 2010
A novel and efficient approach for RC delay evaluation of on-chip VLSI interconnect under current mode signaling technique
R Kar, KR Reddy, AK Mal, AK Bhattacharjee
International Journal of Computer Applications 1 (10), 84-87, 2010
Time-domain smart temperature sensor using current starved inverters and switched ring oscillator-based time-to-digital converter
R Krishna, AK Mal, R Mahapatra
Circuits, Systems, and Signal Processing 39 (4), 1751-1769, 2020
Symbiotic organisms search algorithm for optimal design of CMOS two‐stage op‐amp with nulling resistor and robust bias circuit
S Ghosh, B Prasad De, R Kar, AK Mal
IET Circuits, Devices & Systems 13 (5), 679-688, 2019
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