| Asymmetric NoC architectures for GPU systems AK Ziabari, JL Abellán, Y Ma, A Joshi, D Kaeli Proceedings of the 9th International Symposium on Networks-on-Chip, 1-8, 2015 | 47 | 2015 |
| UMH: A hardware-based unified memory hierarchy for systems with multiple discrete GPUs AK Ziabari, Y Sun, Y Ma, D Schaa, JL Abellán, R Ubal, J Kim, A Joshi, ... ACM Transactions on Architecture and Code Optimization (TACO) 13 (4), 1-25, 2016 | 35 | 2016 |
| Cross-layer co-optimization of network design and chiplet placement in 2.5-D systems A Coskun, F Eris, A Joshi, AB Kahng, Y Ma, A Narayan, V Srinivas IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 29 | 2020 |
| Leveraging thermally-aware chiplet organization in 2.5 D systems to reclaim dark silicon F Eris, A Joshi, AB Kahng, Y Ma, S Mojumder, T Zhang 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 22 | 2018 |
| TAP-2.5 D: A thermally-aware chiplet placement methodology for 2.5 D systems Y Ma, L Delshadtehrani, C Demirkiran, JL Abellan, A Joshi 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 21 | 2021 |
| A Cross-Layer Methodology for Design and Optimization of Networks in 2.5D Systems VS Ayse Coskun, Furkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma Proc. International Conference on Computer-Aided Design (ICCAD), 2018 | 20* | 2018 |
| Cross-layer floorplan optimization for silicon photonic NoCs in many-core systems AK Coskun, A Gu, W Jin, A Joshi, AB Kahng, J Klamkin, Y Ma, J Recchio, ... 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016 | 13 | 2016 |
| Experimental validation of solid oxide fuel cell polarization modeling: An LSM-YSZ/YSZ/Ni-YSZ case study R Wang, Y Lu, Y Ma, Z Sun, S Gopalan, SN Basu, UB Pal Electrochimica Acta 361, 137052, 2020 | 11 | 2020 |
| Mgpu-tsm: A multi-gpu system with truly shared memory SA Mojumder, Y Sun, L Delshadtehrani, Y Ma, T Baruah, JL Abellán, ... arXiv preprint arXiv:2008.02300, 2020 | 5 | 2020 |
| Asymmetric NoC architectures for gpu systems A Kavyan, JL Abellan, Y Ma, A Joshi, D Kaeli Proc. NoCs, 2015 | 5 | 2015 |
| Halcone: A hardware-level timestamp-based cache coherence scheme for multi-gpu systems SA Mojumder, Y Sun, L Delshadtehrani, Y Ma, T Baruah, JL Abellán, ... arXiv preprint arXiv:2007.04292, 2020 | 4 | 2020 |
| Reclaiming Dark Silicon Using Thermally-Aware Chiplet Organization in 2.5D Integrated Systems TZ Ayse Coskun, Furkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma, Saiful ... Proceedings of Boston Area Architecture (BARC) Workshop, 2018 | 1* | 2018 |
| Interconnect and Integration Technology Y Ma, BK Joardar, PP Pande, A Joshi Emerging Computing: From Devices to Systems: Looking Beyond Moore and Von …, 2022 | | 2022 |
| Cross-layer design of thermally-aware 2.5 D systems Y Ma Boston University, 2020 | | 2020 |
| 11.7 Building Resistant Systems: From Temperature Awareness to Attack Resistance F Eris, A Joshi, AB Kahng, Y Ma, S Mojumder, T Zhang | | |
Ajay JoshiProfessor, ECE Department, Boston UniversityGeverifieerd e-mailadres voor bu.edu
