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Nicolas Brunie
Nicolas Brunie
SiFive
Verified email at sifive.com
Title
Cited by
Cited by
Year
Simultaneous branch and warp interweaving for sustained GPU performance
N Brunie, S Collange, G Diamos
Proceedings of the 39th International Symposium on Computer Architecture, 49-60, 2012
1292012
Arithmetic core generation using bit heaps
N Brunie, F de Dinechin, M Istoan, G Sergent, K Illyes, B Popa
Field Programmable Logic and Applications (FPL), 2013 23rd International …, 2013
472013
Code generators for mathematical functions
N Brunie, F De Dinechin, O Kupriianova, C Lauter
2015 IEEE 22nd Symposium on Computer Arithmetic, 66-73, 2015
352015
Modified fused multiply and add for exact low precision product accumulation
N Brunie
2017 IEEE 24th Symposium on Computer Arithmetic (ARITH), 106-113, 2017
282017
A mixed-precision fused multiply and add
N Brunie, F De Dinechin, B De Dinechin
2011 Conference Record of the Forty Fifth Asilomar Conference on Signals …, 2011
252011
Execution efficiency in a single-program, multiple-data processor
S Collange, N Brunie
US Patent App. 13/707,301, 2014
212014
Computing floating-point logarithms with fixed-point operations
J Le Maire, N Brunie, F De Dinechin, JM Muller
2016 IEEE 23nd Symposium on Computer Arithmetic (ARITH), 156-163, 2016
162016
Contributions to computer arithmetic and applications to embedded systems
N Brunie
Ecole normale supérieure de lyon-ENS LYON, 2014
122014
Hardware implementation of floating-point arithmetic
JM Muller, N Brunie, F de Dinechin, CP Jeannerod, M Joldes, V Lefèvre, ...
Handbook of Floating-Point Arithmetic, 267-320, 2018
62018
V. Lef evre, G. Melquiond, N. Revol, and S. Torres, Handbook of Floating-Point Arithmetic
JM Muller, N Brunie, F De Dinechin, CP Jeannerod, M Joldes
Boston, MA, USA: Birkh€ auser, 2018
52018
Software implementation of floating-point arithmetic
JM Muller, N Brunie, F de Dinechin, CP Jeannerod, M Joldes, V Lefèvre, ...
Handbook of Floating-Point Arithmetic, 321-374, 2018
52018
Virtual prototyping of floating point units
G Sarrazin, N Brunie, F Pétrot
Proceedings of the 2016 Workshop on Rapid Simulation and Performance …, 2016
52016
Deep learning inference on the mppa3 manycore processor
B de Dinechin, J Hascot, J Le Maire, N Brunie
Embedded World Confernce 2020 (to appear, 2020
32020
Meta-implementation of vectorized logarithm function in binary floating-point arithmetic
H de Lassus Saint-Geniès, N Brunie, G Revy
2018 IEEE 29th International Conference on Application-specific Systems …, 2018
32018
Meta-implementation of vectorized logarithm function in binary floating-point arithmetic
H de Lassus Saint-Geniès, N Brunie, G Revy
2018 IEEE 29th International Conference on Application-specific Systems …, 2018
32018
Apparatus and method for combining thread warps with compatible execution masks for simultaneous execution and increased lane utilization
N Brunie, S Collange
US Patent 9,851,977, 2017
32017
Blockwise matrix multiplication system
BD De Dinechin, J Le Maire, N Brunie
US Patent 11,169,808, 2021
22021
Definitions and basic notions
JM Muller, N Brunie, F de Dinechin, CP Jeannerod, M Joldes, V Lefèvre, ...
Handbook of Floating-Point Arithmetic, 15-45, 2018
2*2018
Floating-point formats and environment
JM Muller, N Brunie, F de Dinechin, CP Jeannerod, M Joldes, V Lefèvre, ...
Handbook of Floating-Point Arithmetic, 47-93, 2018
2*2018
Reconvergence de contrôle implicite pour les architectures SIMT
N Brunie, C Collange
Revue des Sciences et Technologies de l'Information-Série TSI: Technique et …, 2013
22013
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