A. Mercha
A. Mercha
Technical Director - Technology Platforms Enablement
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Design issues and considerations for low-cost 3-D TSV IC technology
G Van der Plas, P Limaye, I Loi, A Mercha, H Oprins, C Torregiani, S Thijs, ...
IEEE Journal of Solid-State Circuits 46 (1), 293-307, 2010
A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS
D Linten, S Thijs, MI Natarajan, P Wambacq, W Jeamsaksiri, J Ramos, ...
IEEE Journal of Solid-State Circuits 40 (7), 1434-1442, 2005
3D stacked IC demonstration using a through silicon via first approach
J Van Olmen, A Mercha, G Katti, C Huyghebaert, J Van Aelst, E Seppala, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
"Linear kink effect" induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOSFETS
A Mercha, JM Rafi, E Simoen, E Augendre, C Claeys
Electron Devices, IEEE Transactions on 50 (7), 1675-1682, 2003
Planar Bulk MOSFETs Versus FinFETs: An Analog/RF Perspective
V Subramanian, B Parvais, J Borremans, A Mercha, D Linten, P Wambacq, ...
IEEE Transactions on Electron Devices 53 (12), 3071-3079, 2006
Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession
T Chiarella, L Witters, A Mercha, C Kerner, M Rakowski, C Ortolland, ...
Solid-State Electronics 54 (9), 855-860, 2010
Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k/metal gate CMOS performance
A Mercha, G Van der Plas, V Moroz, I De Wolf, P Asimakopoulos, N Minas, ...
2010 International Electron Devices Meeting, 2.2. 1-2.2. 4, 2010
Vertical GAAFETs for the ultimate CMOS scaling
D Yakimets, G Eneman, P Schuddinck, TH Bao, MG Bardon, P Raghavan, ...
IEEE Transactions on Electron Devices 62 (5), 1433-1439, 2015
Multi-gate devices for the 32 nm technology node and beyond
N Collaert, A De Keersgieter, A Dixit, I Ferain, LS Lai, D Lenoble, ...
Solid-State Electronics 52 (9), 1291-1296, 2008
Low-frequency noise behavior of SiO2/HfO2 dual-layer gate dielectric nMOSFETs with different interfacial oxide thickness
E Simoen, A Mercha, L Pantisano, C Claeys, E Young
Electron Devices, IEEE Transactions on 51 (5), 780-784, 2004
Low-power 5 GHz LNA and VCO in 90 nm RF CMOS
D Linten, L Aspemyr, W Jeamsaksiri, J Ramos, A Mercha, S Jenei, S Thijs, ...
2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No …, 2004
Impact of fin width on digital and analog performances of n-FinFETs
V Subramanian, A Mercha, B Parvais, J Loo, C Gustin, M Dehan, ...
Solid-State Electronics 51 (4), 551-559, 2007
3D stacked ICs using Cu TSVs and die to wafer hybrid collective bonding
G Katti, A Mercha, J Van Olmen, C Huyghebaert, A Jourdain, M Stucchi, ...
2009 IEEE international electron devices meeting (IEDM), 1-4, 2009
Low-frequency noise in silicon-on-insulator devices and technologies
E Simoen, A Mercha, C Claeys, N Lukyanchikova
Solid-state electronics 51 (1), 16-37, 2007
Double-gate FinFETs as a CMOS technology downscaling option: An RF perspective
S Nuttinck, B Parvais, G Curatola, A Mercha
IEEE Transactions on electron Devices 54 (2), 279-283, 2007
Dependence of FinFET RF performance on fin width
D Lederer, B Parvais, A Mercha, N Collaert, M Jurczak, JP Raskin, ...
Digest of Papers. 2006 Topical Meeting on Silicon Monolithic Integrated …, 2006
Experimental assessment of self-heating in SOI FinFETs
AJ Scholten, GDJ Smit, RMT Pijper, LF Tiemeijer, HP Tuinhout, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
Strongly anisotropic field ionization of a common deep level in GaAs
A Mircea, A Mitonneau
Journal de Physique Lettres 40 (2), 31-33, 1979
A two-dimensional model for interface coupling in triple-gate transistors
K Akarvardar, A Mercha, S Cristoloveanu, P Gentil, E Simoen, ...
IEEE Transactions on Electron Devices 54 (4), 767-775, 2007
Self-heating on bulk FinFET from 14nm down to 7nm node
D Jang, E Bury, R Ritzenthaler, MG Bardon, T Chiarella, K Miyaguchi, ...
2015 IEEE International Electron Devices Meeting (IEDM), 11.6. 1-11.6. 4, 2015
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