| Activation of logic encrypted chips: Pre-test or post-test? M Yasin, SM Saeed, J Rajendran, O Sinanoglu 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 139-144, 2016 | 77 | 2016 |
| Novel test-mode-only scan attack and countermeasure for compression-based scan architectures SS Ali, SM Saeed, O Sinanoglu, R Karri IEEE transactions on computer-aided design of integrated circuits and …, 2015 | 66 | 2015 |
| New scan-based attack using only the test mode SS Ali, O Sinanoglu, SM Saeed, R Karri 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration …, 2013 | 56 | 2013 |
| CAD-Base: An attack vector into the electronics supply chain K Basu, SM Saeed, C Pilato, M Ashraf, MT Nabeel, K Chakrabarty, R Karri ACM Transactions on Design Automation of Electronic Systems (TODAES) 24 (4 …, 2019 | 47 | 2019 |
| Survey on quantum circuit compilation for noisy intermediate-scale quantum computers: Artificial intelligence to heuristics J Kusyk, SM Saeed, MU Uyar IEEE Transactions on Quantum Engineering 2, 1-16, 2021 | 31 | 2021 |
| A lightweight approach to detect malicious/unexpected changes in the error rates of NISQ computers N Acharya, SM Saeed Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 31 | 2020 |
| Test-mode-only scan attack and countermeasure for contemporary scan architectures SM Saeed, SS Ali, O Sinanoglu, R Karri 2014 International Test Conference, 1-8, 2014 | 26 | 2014 |
| New scan attacks against state-of-the-art countermeasures and DFT SS Ali, O Sinanoglu, SM Saeed, R Karri 2014 IEEE International Symposium on Hardware-Oriented Security and Trust …, 2014 | 25 | 2014 |
| Design for testability support for launch and capture power reduction in launch-off-shift and launch-off-capture testing SM Saeed, O Sinanoglu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (3), 516-521, 2013 | 25 | 2013 |
| Scan attack in presence of mode-reset countermeasure SS Ali, SM Saeed, O Sinanoglu, R Karri 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 230-231, 2013 | 24 | 2013 |
| Probing geometric excitations of fractional quantum hall states on quantum computers A Kirmani, K Bull, CY Hou, V Saravanan, SM Saeed, Z Papić, A Rahmani, ... Physical Review Letters 129 (5), 056801, 2022 | 20 | 2022 |
| Towards reverse engineering reversible logic SM Saeed, X Cui, R Wille, A Zulehner, K Wu, R Drechsler, R Karri arXiv preprint arXiv:1704.08397, 2017 | 18 | 2017 |
| On the difficulty of inserting trojans in reversible computing architectures X Cui, SM Saeed, A Zulehner, R Wille, K Wu, R Drechsler, R Karri IEEE Transactions on Emerging Topics in Computing 8 (4), 960-972, 2018 | 17 | 2018 |
| DfT support for launch and capture power reduction in launch-off-capture testing SM Saeed, O Sinanoglu 2012 17th IEEE European Test Symposium (ETS), 1-6, 2012 | 12 | 2012 |
| Reversible circuits: Ic/ip piracy attacks and countermeasures SM Saeed, A Zulehner, R Wille, R Drechsler, R Karri IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (11 …, 2019 | 11 | 2019 |
| Expedited response compaction for scan power reduction SM Saeed, O Sinanoglu 29th VLSI Test Symposium, 40-45, 2011 | 11 | 2011 |
| IC/IP piracy assessment of reversible logic SM Saeed, X Cui, A Zulehner, R Wille, R Drechsler, K Wu, R Karri 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018 | 10 | 2018 |
| New scan-based attack using only the test mode and an input corruption countermeasure SS Ali, SM Saeed, O Sinanoglu, R Karri VLSI-SoC: At the Crossroads of Emerging Trends: 21st IFIP WG 10.5/IEEE …, 2015 | 9 | 2015 |
| Data-driven reliability models of quantum circuit: From traditional ml to graph neural network V Saravanan, SM Saeed IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022 | 8 | 2022 |
| Test points for online monitoring of quantum circuits N Acharya, M Urbanek, WA De Jong, SM Saeed ACM Journal on Emerging Technologies in Computing Systems (JETC) 18 (1), 1-19, 2021 | 7 | 2021 |
