| Designing systems-on-chip using cores RA Bergamaschi, WR Lee Proceedings of the 37th Annual Design Automation Conference, 420-425, 2000 | 142 | 2000 |
| Automating the design of SoCs using cores RA Bergamaschi, S Bhattacharya, R Wagner, C Fellenz, M Muhlada, ... IEEE Design & Test of Computers, 32-45, 2001 | 134 | 2001 |
| The A to Z of SoCs RA Bergamaschi, J Cohn Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002 | 76 | 2002 |
| Synthesis using path-based scheduling: algorithms and exercises R Camposano, RA Bergamaschi Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE, 450-455, 1990 | 76 | 1990 |
| Methods and arrangements for automatic synthesis of systems-on-chip B Bergamashi, Reinaldo A., D Subhrajit, L Jean-Marc R., W R. US Patent 6,477,691, 2002 | 75* | 2002 |
| Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system RA Bergamaschi, S Raje, I Nair, L Trevillyan Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 5 (1), 82-100, 1997 | 71 | 1997 |
| Exploring power management in multi-core systems R Bergamaschi, G Han, A Buyuktosunoglu, H Patel, I Nair, G Dittmann, ... Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific, 708-713, 2008 | 70 | 2008 |
| State-based power analysis for systems-on-chip RA Bergamaschi, YW Jiang Proceedings of the 40th annual Design Automation Conference, 638-641, 2003 | 68 | 2003 |
| Generalized resource sharing S Raje, RA Bergamaschi Proceedings of the 1997 IEEE/ACM international conference on Computer-aided …, 1997 | 66 | 1997 |
| The effects of false paths in high-level synthesis RA Bergamaschi Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 …, 1991 | 56 | 1991 |
| Modeling and integration of peripheral devices in embedded systems S Wang, S Malik, RA Bergamaschi Proceedings of the conference on Design, Automation and Test in Europe …, 2003 | 55 | 2003 |
| The IBM high-level synthesis system R Camposano, RA Bergamaschi, CE Haynes, M Payer, SM Wu High-Level VLSI Synthesis, 79-104, 1991 | 55 | 1991 |
| Timing analysis in high-level synthesis A Kuehlmann, RA Bergamaschi Proceedings of the 1992 IEEE/ACM international conference on Computer-aided …, 1992 | 54 | 1992 |
| High-level synthesis in an industrial environment RA Bergamaschi, R Connor, L Stok, MZ Moricz, S Prakash, A Kuehlmann, ... IBM Journal of Research and development 39 (1.2), 131-148, 1995 | 53 | 1995 |
| Early analysis tools for system-on-a-chip design JA Darringer, RA Bergamaschi, S Bhattacharya, D Brand, A Herkersdorf, ... IBM Journal of Research and Development 46 (6), 691-707, 2002 | 52 | 2002 |
| Blue Gene/L compute chip: Memory and Ethernet subsystem M Ohmacht, RA Bergamaschi, S Bhattacharya, A Gara, ME Giampapa, ... IBM Journal of Research and Development 49 (2.3), 255-264, 2005 | 44 | 2005 |
| Behavioral network graph: unifying the domains of high-level and logic synthesis RA Bergamaschi Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 213-218, 1999 | 37 | 1999 |
| Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems N Dhanwada, RA Bergamaschi, WW Dungan, I Nair, P Gramann, ... Design Automation for Embedded Systems 10 (2), 105-125, 2005 | 32 | 2005 |
| Bridging the domains of high-level and logic synthesis RA Bergamaschi Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2002 | 30 | 2002 |
| Allocation algorithms based on path analysis RA Bergamaschi, R Camposano, M Payer Integration, the VLSI journal 13 (3), 283-299, 1992 | 30 | 1992 |
