Odysseas Zografos
Odysseas Zografos
R&D engineer, imec, Leuven, Belgium
Geverifieerd e-mailadres voor imec.be - Homepage
TitelGeciteerd doorJaar
Design and benchmarking of hybrid CMOS-spin wave device circuits compared to 10nm CMOS
O Zografos, B Sorée, A Vaysset, S Cosemans, L Amaru, PE Gaillardon, ...
2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO), 686-689, 2015
262015
Non-volatile spin wave majority gate at the nanoscale
O Zografos, S Dutta, M Manfrini, A Vaysset, B Sorée, A Naeemi, ...
AIP Advances 7 (5), 056020, 2017
162017
Spintronic majority gates
IP Radu, O Zografos, A Vaysset, F Ciubotaru, J Yan, J Swerts, D Radisic, ...
2015 IEEE International Electron Devices Meeting (IEDM), 32.5. 1-32.5. 4, 2015
162015
Inversion optimization in majority-inverter graphs
E Testa, M Soeken, O Zografos, L Amaru, P Raghavan, R Lauwereins, ...
2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2016
112016
System-level assessment and area evaluation of spin wave logic circuits
O Zografos, P Raghavan, L Amarú, B Sorée, R Lauwereins, I Radu, ...
2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2014
112014
Exchange-driven magnetic logic
O Zografos, M Manfrini, A Vaysset, B Sorée, F Ciubotaru, C Adelmann, ...
Scientific reports 7 (1), 12154, 2017
102017
Inverter propagation and fan-out constraints for beyond-CMOS majority-based technologies
E Testa, O Zografos, M Soeken, A Vaysset, M Manfrini, R Lauwereins, ...
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 164-169, 2017
102017
Majority logic synthesis for spin wave technology
O Zografos, L Amaru, PE Gaillardon, P Raghavan, G De Micheli
2014 17th Euromicro Conference on Digital System Design, 691-694, 2014
102014
Novel grid-based power routing scheme for regular controllable-polarity FET arrangements
O Zografos, PE Gaillardon, G De Micheli
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1416-1419, 2014
102014
Wave pipelining for majority-based beyond-CMOS technologies
O Zografos, A De Meester, E Testa, M Soeken, PE Gaillardon, ...
Proceedings of the Conference on Design, Automation & Test in Europe, 1306-1311, 2017
82017
Interconnected magnetic tunnel junctions for spin-logic applications
M Manfrini, A Vaysset, D Wan, E Raymenants, J Swerts, S Rao, ...
AIP Advances 8 (5), 055921, 2018
62018
Proposal for nanoscale cascaded plasmonic majority gates for non-Boolean computation
S Dutta, O Zografos, S Gurunarayanan, I Radu, B Soree, F Catthoor, ...
Scientific reports 7 (1), 17866, 2017
62017
Heterogeneous nano-to wide-scale co-integration of beyond-Si and Si CMOS devices to enhance future electronics
A Thean, N Collaert, IP Radu, N Waldron, C Merckling, L Witters, R Loo, ...
ECS Transactions 66 (4), 3-14, 2015
62015
Chain of magnetic tunnel junctions as a spintronic memristor
E Raymenants, A Vaysset, D Wan, M Manfrini, O Zografos, O Bultynck, ...
Journal of Applied Physics 124 (15), 152116, 2018
52018
Area and routing efficiency of SWD circuits compared to advanced CMOS
O Zografos, P Raghavan, Y Sherazi, A Vaysset, F Ciubatoru, B Sorée, ...
2015 International Conference on IC Design & Technology (ICICDT), 1-4, 2015
52015
ESD characterization of high mobility SiGe quantum well and ge devices for future CMOS scaling
G Hellings, D Linten, S Thijs, SH Chen, L Witters, J Mitard, O Zografos, ...
Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2012, 1-6, 2012
52012
Exact synthesis for logic synthesis applications with complex constraints
E Testa, M Soeken, O Zografos, F Catthoor, G De Micheli
Proceedings of the 26th International Workshop on Logic & Synthesis (IWLS), 2017
42017
ESD performance of high mobility SiGe quantum well bulk FinFET diodes and pMOS devices
D Linten, G Hellings, SH Chen, O Zografos, M Scholz, A Veloso, ...
2013 35th Electrical Overstress/Electrostatic Discharge Symposium, 1-8, 2013
42013
First experimental demonstration of a scalable linear majority gate based on spin waves
F Ciubotaru, G Talmelli, T Devolder, O Zografos, M Heyns, C Adelmann, ...
2018 IEEE International Electron Devices Meeting (IEDM), 36.1. 1-36.1. 4, 2018
32018
Design and simulation of plasmonic interference-based majority gate
J Doevenspeck, O Zografos, S Gurunarayanan, R Lauwereins, ...
AIP Advances 7 (6), 065116, 2017
32017
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Artikelen 1–20