|Single-crystalline Si stacked array (STAR) NAND flash memory|
JG Yun, G Kim, JE Lee, Y Kim, WB Shim, JH Lee, H Shin, JD Lee, ...
IEEE Transactions on Electron Devices 58 (4), 1006-1014, 2011
|3D stacked array having cut-off gate line and fabrication method thereof|
B Park, S Cho, WB Shim
US Patent 8,786,004, 2014
|Program/erase model of nitride-based NAND-type charge trap flash memories|
DH Kim, S Cho, DH Li, JG Yun, JH Lee, GS Lee, Y Kim, WB Shim, ...
Japanese Journal of Applied Physics 49 (8R), 084301, 2010
|Drain-erase scheme in ferroelectric field effect transistor—Part II: 3-D-NAND architecture for in-memory computing|
P Wang, W Shim, Z Wang, J Hur, S Datta, AI Khan, S Yu
IEEE Transactions on Electron Devices 67 (3), 962-967, 2020
|Drain–erase scheme in ferroelectric field-effect transistor—Part I: Device characterization|
P Wang, Z Wang, W Shim, J Hur, S Datta, AI Khan, S Yu
IEEE Transactions on Electron Devices 67 (3), 955-961, 2020
|A Vertical 4-Bit SONOS Flash Memory and a Unique 3-D Vertical nor Array Structure|
Y Kim, IH Park, S Cho, JG Yun, JH Lee, DH Kim, GS Lee, SH Park, ...
IEEE transactions on nanotechnology 9 (1), 70-77, 2009
|Arch NAND flash memory array with improved virtual source/drain performance|
W Kim, JH Lee, JG Yun, S Cho, DH Li, Y Kim, DH Kim, GS Lee, SH Park, ...
IEEE electron device letters 31 (12), 1374-1376, 2010
|A charge trap folded NAND flash memory device with band-gap-engineered storage node|
S Cho, WB Shim, Y Kim, JG Yun, JD Lee, H Shin, JH Lee, BG Park
IEEE Transactions on Electron Devices 58 (2), 288-295, 2010
|Investigation of read disturb and bipolar read scheme on multilevel RRAM-based deep learning inference engine|
W Shim, Y Luo, JS Seo, S Yu
IEEE Transactions on Electron Devices 67 (6), 2318-2323, 2020
|Cone-type SONOS flash memory|
GS Lee, JH Lee, IH Park, S Cho, JG Yun, DH Li, DH Kim, Y Kim, SH Park, ...
IEEE electron device letters 30 (12), 1332-1334, 2009
|Impact of read disturb on multilevel RRAM based inference engine: Experiments and model prediction|
W Shim, Y Luo, J Seo, S Yu
2020 IEEE International Reliability Physics Symposium (IRPS), 1-5, 2020
|Nonvolatile memory device, erase method thereof and memory system including the same|
US Patent 9,514,828, 2016
|Method of detecting erase fail word-line in non-volatile memory device|
US Patent 9,704,596, 2017
|Room-Temperature Operation of a Single-Electron Transistor Made by Oxidation Process Using the Recessed Channel Structure|
JE Lee, G Kim, KK Wan, WB Shim, JH Lee, KC Kang, JG Yun, JH Lee, ...
Japanese Journal of Applied Physics 49 (11R), 115202, 2010
|Technological design of 3D NAND-based compute-in-memory architecture for GB-scale deep neural network|
W Shim, S Yu
IEEE Electron Device Letters 42 (2), 160-163, 2020
|Two-step write–verify scheme and impact of the read noise in multilevel RRAM-based inference engine|
W Shim, J Seo, S Yu
Semiconductor Science and Technology 35 (11), 115026, 2020
|Stacked gated twin-bit (SGTB) SONOS memory device for high-density flash memory|
WB Shim, S Cho, JH Lee, DH Li, DH Kim, GS Lee, Y Kim, SH Park, W Kim, ...
IEEE transactions on nanotechnology 11 (2), 307-313, 2011
|Memory device, memory system, method of operating the memory device, and method of operating the memory system|
SS Park, Y Kim, WB Shim
US Patent 9,824,765, 2017
|Highly scalable 3-D NAND-NOR hybrid-type dual bit per cell flash memory devices with an additional cut-off gate|
S Cho, WB Shim, IH Park, Y Kim, BG Park
Journal of the Korean Physical Society 56 (1), 137-141, 2010
|Locally-separated vertical channel SONOS flash memory (LSVC SONOS) for multi-storage and multi-level operation|
Y Kim, JG Yun, IH Park, S Cho, JH Lee, SH Park, DH Lee, DH Kim, ...
2008 IEEE Silicon Nanoelectronics Workshop, 1-2, 2008