A 28-Gb/s receiver with self-contained adaptive equalization and sampling point control using stochastic sigma-tracking eye-opening monitor H Won, JY Lee, T Yoon, K Han, S Lee, J Park, HM Bae
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (3), 664-674, 2016
69 2016 6.4 A 56Gb/s 7.7 mW/Gb/s PAM-4 wireline transceiver in 10nm FinFET using MM-CDR-based ADC timing skew control and low-power DSP with approximate multiplier BJ Yoo, DH Lim, H Pang, JH Lee, SY Baek, N Kim, DH Choi, YH Choi, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 122-124, 2020
47 2020 A 0.87 W transceiver IC for 100 gigabit Ethernet in 40 nm CMOS H Won, T Yoon, J Han, JY Lee, JH Yoon, T Kim, JS Lee, S Lee, K Han, ...
IEEE Journal of Solid-State Circuits 50 (2), 399-413, 2014
34 2014 An automatic loop gain control algorithm for bang-bang CDRs SW Kwon, JY Lee, J Lee, K Han, T Kim, S Lee, JS Lee, T Yoon, H Won, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 62 (12), 2817-2828, 2015
16 2015 A 20Gb/s transceiver with framed-pulsewidth modulation in 40nm CMOS S Jeon, W Kwon, T Yoon, JH Yoon, K Kwon, J Yang, HM Bae
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 270-272, 2018
11 2018 A Power-and-Area Efficient JY Lee, K Han, T Yoon, T Kim, SE Lee, JS Lee, J Park, HM Bae
IEEE Journal of Solid-State Circuits 51 (10), 2475-2484, 2016
8 2016 A Framed-Pulsewidth Modulation Transceiver for High-Speed Broadband Communication Links S Jeon, W Kwon, JH Yoon, T Yoon, K Kwon, J Yang, HM Bae
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (8), 2825-2835, 2020
2 2020 A 100-GbE reverse gearbox IC in 40nm CMOS for supporting legacy 10-and 40-GbE standards T Yoon, JY Lee, K Han, J Lee, S Lee, T Kim, H Won, J Park, HM Bae
2015 Symposium on VLSI Circuits (VLSI Circuits), C212-C213, 2015
2 2015 Phase interpolator based output waveform synthesizer for low-power broadband transmitter HM Bae, TH Yoon, JH Yoon
US Patent 8,917,116, 2014
2 2014 A 103.125-Gb/s reverse gearbox IC in 40-nm CMOS for supporting legacy 10-and 40-GbE links T Yoon, JY Lee, J Lee, K Han, JS Lee, S Lee, T Kim, J Han, H Won, J Park, ...
IEEE Journal of Solid-State Circuits 52 (3), 688-703, 2017
1 2017 Low-power CML-less transmitter architecture HM Bae, TH Yoon, JH Park, TH Kim
US Patent 9,419,736, 2016
1 2016 Low-power and all-digital phase interpolator-based clock and data recovery architecture HM Bae, TH Yoon, JY Lee
US Patent 9,166,605, 2015
1 2015 