A 6-b 4.1-GS/s flash ADC with time-domain latch interpolation in 90-nm CMOS JI Kim, W Kim, ST Ryu IEEE Journal of Solid-State Circuits 48 (6), 1429-1441, 2013 | 74 | 2013 |
A 65 nm CMOS 7b 2 GS/s 20.7 mW flash ADC with cascaded latch interpolation JI Kim, DR Oh, DS Jo, ST Ryu IEEE Journal of Solid-State Circuits 50 (10), 2319-2330, 2015 | 56 | 2015 |
A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration DR Oh, JI Kim, DS Jo, WC Kim, DJ Chang, ST Ryu IEEE Journal of Solid-State Circuits 54 (1), 288-297, 2018 | 40 | 2018 |
A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration CK Lee, W Kim, JI Kim, HK Hong, GG Oh, CH Lee, M Choi, HJ Park, ... 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 281-284, 2013 | 31 | 2013 |
A time-interleaved flash-SAR architecture for high speed A/D conversion BRS Sung, SH Cho, CK Lee, JI Kim, ST Ryu 2009 IEEE International Symposium on Circuits and Systems, 984-987, 2009 | 27 | 2009 |
A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS DR Oh, JI Kim, MJ Seo, JG Kim, ST Ryu ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015 | 26 | 2015 |
A time-domain latch interpolation technique for low power flash ADCs JI Kim, W Kim, B Sung, ST Ryu 2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2011 | 13 | 2011 |