Zigzag super cut-off CMOS (ZSCCMOS) block activation with self-adaptive voltage level controller: An alternative to clock-gating scheme in leakage dominant era KS Min, H Kawaguchi, T Sakurai
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of …, 2003
157 2003 New memristor-based crossbar array architecture with 50-% area reduction and 48-% power saving for matrix-vector multiplication of analog neuromorphic computing SN Truong, KS Min
JSTS: Journal of Semiconductor Technology and Science 14 (3), 356-363, 2014
136 2014 Neuromorphic crossbar circuit with nanoscale filamentary-switching binary memristors for speech recognition SN Truong, SJ Ham, KS Min
Nanoscale research letters 9, 1-9, 2014
88 2014 Two-step write scheme for reducing sneak-path leakage in complementary memristor array CM Jung, JM Choi, KS Min
IEEE transactions on nanotechnology 11 (3), 611-618, 2012
86 2012 Self-adaptive write circuit for low-power and variation-tolerant memristors KH Jo, CM Jung, KS Min, SM Kang
IEEE Transactions on Nanotechnology 9 (6), 675-678, 2010
73 2010 Charge pump circuit KS Min
US Patent 6,734,717, 2004
60 2004 Two orders of magnitude leakage power reduction of low voltage SRAMs by row-by-row dynamic V/sub dd/control (RRDV) scheme K Kanda, T Miyazaki, MK Sik, H Kawaguchi, T Sakurai
15th annual IEEE international ASIC/SOC conference, 381-385, 2002
57 2002 Zero-sleep-leakage flip-flop circuit with conditional-storing memristor retention latch CM Jung, KH Jo, ES Lee, HM Vo, KS Min
IEEE Transactions on Nanotechnology 11 (2), 360-366, 2011
53 2011 A memristor crossbar array of titanium oxide for non-volatile memory and neuromorphic applications H Abbas, Y Abbas, SN Truong, KS Min, MR Park, J Cho, TS Yoon, ...
Semiconductor Science and Technology 32 (6), 065014, 2017
48 2017 A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs YJ Jeon, JH Lee, HC Lee, KW Jin, KS Min, JY Chung, HJ Park
IEEE journal of solid-state circuits 39 (11), 2087-2092, 2004
48 2004 New twin crossbar architecture of binary memristors for low-power image recognition with discrete cosine transform SN Truong, SH Shin, SD Byeon, JS Song, KS Min
IEEE Transactions on Nanotechnology 14 (6), 1104-1111, 2015
44 2015 CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits KS Min, JH AHN
IEICE transactions on electronics 85 (1), 225-229, 2002
43 2002 Leakage-suppressed clock-gating circuit with zigzag super cut-off cmos (zsccmos) for leakage-dominant sub-70-nm and sub-1-vv/sub dd/lsis KS Min, HD Choi, HY Choi, H Kawaguchi, T Sakurai
IEEE transactions on very large scale integration (VLSI) systems 14 (4), 430-435, 2006
35 2006 A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs JK Wee, KS Min, JT Park, SP Lee, YH Kim, TH Yang, JD Joo, JY Chung
IEEE Journal of Solid-State Circuits 37 (2), 251-254, 2002
35 2002 A fast pump-down V/sub BB/generator for sub-1.5-V DRAMs KS Min, JY Chung
IEEE Journal of Solid-State Circuits 36 (7), 1154-1157, 2001
35 2001 Asymmetrical training scheme of binary-memristor-crossbar-based neural networks for energy-efficient edge-computing nanoscale systems KV Pham, SB Tran, TV Nguyen, KS Min
Micromachines 10 (2), 141, 2019
34 2019 Low‐Power Self‐Rectifying Memristive Artificial Neural Network for Near Internet‐of‐Things Sensor Computing S Choi, Y Kim, T Van Nguyen, WH Jeong, KS Min, BJ Choi
Advanced Electronic Materials 7 (6), 2100050, 2021
33 2021 Memristor crossbar array for binarized neural networks Y Kim, WH Jeong, SB Tran, HC Woo, J Kim, CS Hwang, KS Min, BJ Choi
Aip Advances 9 (4), 2019
32 2019 Memristor binarized neural networks K Van Pham, T Van Nguyen, SB Tran, HK Nam, MJ Lee, BJ Choi, ...
J. Semicond. Technol. Sci 18 (5), 568-588, 2018
32 2018 Low-Power SJ Ham, HS Mo, KS Min
IEEE transactions on nanotechnology 12 (5), 851-857, 2013
31 2013 