Rajendra Bishnoi
Rajendra Bishnoi
TU-Delft
Geverifieerd e-mailadres voor kit.edu
TitelGeciteerd doorJaar
Evaluation of hybrid memory technologies using SOT-MRAM for on-chip cache hierarchy
F Oboril, R Bishnoi, M Ebrahimi, MB Tahoori
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
862015
Ultra-fast and high-reliability SOT-MRAM: From cache replacement to normally-off computing
G Prenat, K Jabeur, P Vanhauwaert, G Di Pendina, F Oboril, R Bishnoi, ...
IEEE Transactions on Multi-Scale Computing Systems 2 (1), 49-60, 2015
692015
Read disturb fault detection in STT-MRAM
R Bishnoi, M Ebrahimi, F Oboril, MB Tahoori
2014 International Test Conference, 1-7, 2014
492014
Avoiding unnecessary write operations in STT-MRAM for low power implementation
R Bishnoi, F Oboril, M Ebrahimi, MB Tahoori
Fifteenth International Symposium on Quality Electronic Design, 548-553, 2014
472014
Architectural aspects in design and analysis of SOT-based memories
R Bishnoi, M Ebrahimi, F Oboril, MB Tahoori
2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 700-707, 2014
362014
Improving Write Performance for STT-MRAM
R Bishnoi, M Ebrahimi, F Oboril, M Tahoori
IEEE Transaction on Magnetics 52 (8), 1-11, 2016
302016
Asynchronous asymmetrical write termination (AAWT) for a low power STT-MRAM
R Bishnoi, M Ebrahimi, F Oboril, MB Tahoori
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
302014
Layout-based modeling and mitigation of multiple event transients
M Ebrahimi, H Asadi, R Bishnoi, MB Tahoori
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
272015
Design of defect and fault-tolerant nonvolatile spintronic flip-flops
R Bishnoi, F Oboril, MB Tahoori
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (4 …, 2016
262016
Non-volatile non-shadow flip-flop using spin orbit torque for efficient normally-off computing
R Bishnoi, F Oboril, MB Tahoori
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 769-774, 2016
172016
Self-timed read and write operations in STT-MRAM
R Bishnoi, F Oboril, M Ebrahimi, MB Tahoori
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (5 …, 2015
142015
Inkjet-printed EGFET-based physical unclonable function—Design, evaluation, and fabrication
AT Erozan, GC Marques, MS Golanbari, R Bishnoi, S Dehm, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (12 …, 2018
112018
Fault tolerant non-volatile spintronic flip-flop
R Bishnoi, F Oboril, MB Tahoori
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 261-264, 2016
102016
A cross-layer analysis of soft error, aging and process variation in near threshold computing
A Gebregiorgis, S Kiamehr, F Oboril, R Bishnoi, MB Tahoori
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 205-210, 2016
102016
Low-power multi-port memory architecture based on spin orbit torque magnetic devices
R Bishnoi, F Oboril, MB Tahoori
2016 International Great Lakes Symposium on VLSI (GLSVLSI), 409-414, 2016
92016
Exploiting STT-MRAM for approximate computing
N Sayed, F Oboril, A Shirvanian, R Bishnoi, MB Tahoori
2017 22nd IEEE European Test Symposium (ETS), 1-6, 2017
82017
Leveraging systematic unidirectional error-detecting codes for fast STT-MRAM cache
N Sayed, F Oboril, R Bishnoi, MB Tahoori
2017 IEEE 35th VLSI Test Symposium (VTS), 1-6, 2017
82017
VAET-STT: A variation aware estimator tool for STT-MRAM based memories
SM Nair, R Bishnoi, MS Golanbari, F Oboril, MB Tahoori
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
82017
Opportunistic write for fast and reliable STT-MRAM
N Sayed, M Ebrahimi, R Bishnoi, MB Tahoori
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
82017
VAET-STT: Variation aware STT-MRAM analysis and design space exploration tool
SM Nair, R Bishnoi, MS Golanbari, F Oboril, F Hameed, MB Tahoori
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
72017
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Artikelen 1–20