Jean Da Rolt
Jean Da Rolt
Geverifieerd e-mailadres voor bento.ifrs.edu.br
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Test versus security: Past and present
J Da Rolt, A Das, G Di Natale, ML Flottes, B Rouzeyre, I Verbauwhede
IEEE Transactions on Emerging topics in Computing 2 (1), 50-62, 2014
812014
Are advanced DfT structures sufficient for preventing scan-attacks?
J Da Rolt, G Di Natale, ML Flottes, B Rouzeyre
2012 IEEE 30th VLSI Test Symposium (VTS), 246-251, 2012
662012
New security threats against chips containing scan chain structures
J Da Rolt, G Di Natale, ML Flottes, B Rouzeyre
2011 IEEE International Symposium on Hardware-Oriented Security and Trust …, 2011
642011
A novel differential scan attack on advanced DFT structures
JD Rolt, GD Natale, ML Flottes, B Rouzeyre
ACM Transactions on Design Automation of Electronic Systems (TODAES) 18 (4 …, 2013
532013
Secure JTAG implementation using Schnorr protocol
A Das, J Da Rolt, S Ghosh, S Seys, S Dupuis, G Di Natale, ML Flottes, ...
Journal of Electronic Testing 29 (2), 193-209, 2013
352013
A new scan attack on rsa in presence of industrial countermeasures
J Da Rolt, A Das, G Di Natale, ML Flottes, B Rouzeyre, I Verbauwhede
International Workshop on Constructive Side-Channel Analysis and Secure …, 2012
342012
Thwarting scan-based attacks on secure-ICs with on-chip comparison
J Da Rolt, G Di Natale, ML Flottes, B Rouzeyre
IEEE transactions on very large scale integration (VLSI) systems 22 (4), 947-951, 2013
322013
A smart test controller for scan chains in secure circuits
J Da Rolt, G Di Natale, ML Flottes, B Rouzeyre
2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 228-229, 2013
232013
A scan-based attack on elliptic curve cryptosystems in presence of industrial design-for-testability structures
J Da Rolt, A Das, G Di Natale, ML Flottes, B Rouzeyre, I Verbauwhede
2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2012
222012
On-chip test comparison for protecting confidential data in secure ICs
J Da Rolt, G Di Natale, ML Flottes, B Rouzeyre
2012 17th IEEE European Test Symposium (ETS), 1-1, 2012
62012
Adaptive low-power architecture for high-performance and reliable embedded computing
RR Ferreira, J Da Rolt, GL Nazar, AF Moreira, L Carro
2014 44th Annual IEEE/IFIP International Conference on Dependable Systems …, 2014
52014
Scan attacks on side-channel and fault attack resistant public-key implementations
J Da Rolt, A Das, S Ghosh, G Di Natale, ML Flottes, B Rouzeyre, ...
Journal of Cryptographic Engineering 2 (4), 207-219, 2012
42012
Permanent fault detection and diagnosis in the lightweight dual modular redundancy architecture
RR Ferreira, E Sanchez, J Da Rolt, GL Nazar, AF Moreira, L Carro, ...
2015 16th Latin-American Test Symposium (LATS), 1-6, 2015
22015
Reliable execution of statechart-generated correct embedded software under soft errors
RR Ferreira, T Klotz, T Vörtler, J da Rolt, GL Nazar, AF Moreira, L Carro, ...
17th International Symposium on Design and Diagnostics of Electronic …, 2014
2014
2013 JETTA-TTTC Best Paper Award
A Das, J Da Rolt, S Ghosh, S Seys, S Dupuis, G Di Natale, BR Flottes, ...
J Electron Test 30, 639-640, 2014
2014
On-Chip Comparison for Testing Secure ICs
J Da Rolt, G Di Natale, ML Flottes, B Rouzeyre
DCIS'2012: Conference on Design of Circuits and Integrated Systems, 112-117, 2012
2012
New side-channel attack against scan chains
J Da Rolt, ML Flottes, G Di Natale, B Rouzeyre
9th CryptArchi Workshop (2011), 2, 2011
2011
2 Special Issue on Emerging Nanoscale Architectures for Hardware Security, Trust, and Reliability: Part 1 by R. Karri and M. Potkonjak 4 On-Chip Nanoscale Capacitor Decoupling …
M Mayhew, R Muresan, J Kong, F Koushanfar, L Bossuet, XT Ngo, ...
New scan attacks against secure chips
J Da Rolt, G Di Natale, ML Flottes, B Rouzeyre
Preventing scan-based attacks on secure-ICs with on-chip comparison
J Da Rolt, G Di Natale, ML Flottes, B Rouzeyre
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Artikelen 1–20