Renyuan ZHANG
Renyuan ZHANG
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Cited by
Cited by
CMOS supporting circuitries for nano-oscillator-based associative memories
T Shibata, R Zhang, SP Levitan, DE Nikonov, GI Bourianoff
2012 13th International Workshop on Cellular Nanoscale Networks and their …, 2012
Fully parallel self-learning analog support vector machine employing compact gaussian generation circuits
R Zhang, T Shibata
Japanese Journal of Applied Physics 51 (4S), 04DE10, 2012
A low voltage CMOS rectifier for wirelessly powered devices
Q Li, R Zhang, Z Huang, Y Inoue
Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010
Training low-latency spiking neural network through knowledge distillation
S Takuya, R Zhang, Y Nakashima
2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 1-3, 2021
Design of programmable analog calculation unit by implementing support vector regression for approximate computing
R Zhang, N Uetake, T Nakada, Y Nakashima
IEEE Micro 38 (6), 73-82, 2018
STT-BSNN: An in-memory deep binary spiking neural network based on STT-MRAM
VT Nguyen, QK Trinh, R Zhang, Y Nakashima
IEEE Access 9, 151373-151385, 2021
A low breakdown-voltage charge pump based on Cockcroft-Walton structure
R Zhang, Z Huang, Y Inoue
2009 IEEE 8th International Conference on ASIC, 328-331, 2009
An analog on-line-learning K-means processor employing fully parallel self-converging circuitry
R Zhang, T Shibata
Analog Integrated Circuits and Signal Processing 75, 267-277, 2013
Daisy-chained systolic array and reconfigurable memory space for narrow memory bandwidth
J Iwamoto, Y Kikutani, R Zhang, Y Nakashima
IEICE TRANSACTIONS on Information and Systems 103 (3), 578-589, 2020
Multi-tier platform for cognizing massive electroencephalogram
Z Chen, L Zhu, Z Yang, R Zhang
arXiv preprint arXiv:2204.09840, 2022
A multi-grained reconfigurable accelerator for approximate computing
Y Kan, M Wu, R Zhang, Y Nakashima
2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 90-95, 2020
Robust and low-power digitally programmable delay element designs employing neuron-MOS mechanism
R Zhang, M Kaneko
ACM Transactions on Design Automation of Electronic Systems (TODAES) 20 (4 …, 2015
A 16-valued logic FPGA architecture employing analog memory circuit
R Zhang, M Kaneko
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 718-721, 2016
A vlsi hardware implementation study of svdd algorithm using analog gaussian-cell array for on-chip learning
R Zhang, T Shibata
2012 13th International Workshop on Cellular Nanoscale Networks and their …, 2012
A transformer-based spatial-temporal sleep staging model through raw EEG
G Shi, Z Chen, R Zhang
2021 International Conference on High Performance Big Data and Intelligent …, 2021
A programmable calculation unit employing memcapacitor-based neuromorphic circuit
Y Chen, J Zhang, Y Zhang, R Zhang, M Kimura, Y Nakashima
2019 17th IEEE International New Circuits and Systems Conference (NEWCAS), 1-4, 2019
Adaptive spike-like representation of eeg signals for sleep stages scoring
L Zhu, Z Yang, K Odani, G Shi, Y Kan, Z Chen, R Zhang
2022 44th Annual International Conference of the IEEE Engineering in …, 2022
A memcapacitive spiking neural network with circuit nonlinearity-aware training
R Oshio, T Sugahara, A Sawada, M Kimura, R Zhang, Y Nakashima
2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 1-6, 2022
MuGRA: A scalable multi-grained reconfigurable accelerator powered by elastic neural network
Y Kan, M Wu, R Zhang, Y Nakashima
IEEE Transactions on Circuits and Systems I: Regular Papers 69 (1), 258-271, 2021
An efficient ReRAM-based inference accelerator for convolutional neural networks via activation reuse
Y Chen, J Zhang, Y Xu, Y Zhang, R Zhang, Y Nakashima
IEICE Electronics Express 16 (18), 20190396-20190396, 2019
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