David Bol
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Interests and limitations of technology scaling for subthreshold logic
D Bol, R Ambroise, D Flandre, JD Legat
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (10 …, 2009
SleepWalker: A 25-MHz 0.4-V Sub-mm² 7µW/MHz Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes
D Bol, J De Vos, C Hocquet, F Botman, F Durvaux, S Boyd, D Flandre, ...
IEEE Journal of Solid-State Circuits 48 (1), 20-32, 2013
Towards green cryptography: a comparison of lightweight ciphers from the energy viewpoint
S Kerckhof, F Durvaux, C Hocquet, D Bol, FX Standaert
International Workshop on Cryptographic Hardware and Embedded Systems, 390-407, 2012
Analysis and minimization of practical energy in 45nm subthreshold logic circuits
D Bol, R Ambroise, D Flandre, JD Legat
2008 IEEE International Conference on Computer Design, 294-300, 2008
Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits
D Bol, D Flandre, JD Legat
Proceedings of the 2009 ACM/IEEE international symposium on Low power …, 2009
A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes
D Bol, J De Vos, C Hocquet, F Botman, F Durvaux, S Boyd, D Flandre, ...
2012 IEEE International Solid-State Circuits Conference, 490-492, 2012
A 0.086-mm 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS
C Frenkel, M Lefebvre, JD Legat, D Bol
IEEE transactions on biomedical circuits and systems 13 (1), 145-158, 2018
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic
D Bol, D Kamel, D Flandre, JD Legat
Proceedings of the 2009 ACM/IEEE international symposium on Low power …, 2009
Robust and energy-efficient ultra-low-voltage circuit design under timing constraints in 65/45 nm CMOS
D Bol
Journal of Low Power Electronics and Applications 1 (1), 1, 2011
8.4 A 0.33 V/-40° C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing
S Clerc, M Saligane, F Abouzeid, M Cochet, JM Daveau, C Bottoni, D Bol, ...
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
Bellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37 V for processing-intensive wireless sensor nodes
F Botman, J De Vos, S Bernard, F Stas, JD Legat, D Bol
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1207-1210, 2014
Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags
C Hocquet, D Kamel, F Regazzoni, JD Legat, D Flandre, D Bol, ...
Journal of Cryptographic Engineering 1 (1), 79-86, 2011
Green SoCs for a sustainable Internet-of-Things
D Bol, J De Vos, F Botman, G de Streel, S Bernard, D Flandre, JD Legat
2013 IEEE Faible Tension Faible Consommation, 1-4, 2013
SleepTalker: A ULV 802.15. 4a IR-UWB transmitter SoC in 28-nm FDSOI achieving 14 pJ/b at 27 Mb/s with channel selection based on adaptive FBB and digitally programmable pulse …
G de Streel, F Stas, T Gurné, F Durant, C Frenkel, A Cathelin, D Bol
IEEE Journal of Solid-State Circuits 52 (4), 1163-1177, 2017
A sizing methodology for on-chip switched-capacitor DC/DC converters
J De Vos, D Flandre, D Bol
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (5), 1597-1606, 2013
Exploring the feasibility of low cost fault injection attacks on sub-threshold devices through an example of a 65nm aes implementation
A Barenghi, C Hocquet, D Bol, FX Standaert, F Regazzoni, I Koren
International Workshop on Radio Frequency Identification: Security and …, 2011
Impact of technology scaling on digital subthreshold circuits
D Bol, R Ambroise, D Flandre, JD Legat
2008 IEEE Computer Society Annual Symposium on VLSI, 179-184, 2008
Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology
G de Streel, D Bol
International Symposium on Low Power Electronics and Design (ISLPED), 255-260, 2013
A capacitance-to-frequency converter with on-chip passivated microelectrodes for bacteria detection in saline buffers up to 575 MHz
N Couniot, D Bol, O Poncelet, LA Francis, D Flandre
IEEE Transactions on Circuits and Systems II: Express Briefs 62 (2), 159-163, 2014
A 65-nm 0.5-V 17-pJ/frame. pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range
D Bol, G de Streel, F Botman, AK Lusala, N Couniot
2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2, 2014
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