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Xin Zhao
Xin Zhao
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3D-MAPS: 3D massively parallel processor with stacked memory
SK Lim, SK Lim
Design for High Performance, Low Power, and Reliable 3D Integrated Circuits …, 2013
2212013
Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory
MB Healy, K Athikulwongse, R Goel, MM Hossain, DH Kim, YJ Lee, ...
IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010
1002010
Low-power and reliable clock network design for through-silicon via (TSV) based 3D ICs
X Zhao, J Minz, SK Lim
IEEE Transactions on Components, Packaging and Manufacturing Technology 1 (2 …, 2010
972010
Buffered clock tree synthesis for 3D ICs under thermal variations
J Minz, X Zhao, SK Lim
2008 Asia and South Pacific Design Automation Conference, 504-509, 2008
952008
Pre-bond testable low-power clock tree design for 3D stacked ICs
X Zhao, DL Lewis, HHS Lee, SK Lim
Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009
822009
Design and analysis of 3D-MAPS (3D massively parallel processor with stacked memory)
DH Kim, K Athikulwongse, MB Healy, MM Hossain, M Jung, I Khorosh, ...
IEEE Transactions on Computers 64 (1), 112-125, 2013
802013
Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs
X Zhao, SK Lim
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 175-180, 2010
472010
Low-power clock tree design for pre-bond testing of 3-D stacked ICs
X Zhao, DL Lewis, HHS Lee, SK Lim
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011
462011
Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs
X Zhao, Y Wan, M Scheuermann, SK Lim
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 363-370, 2013
372013
Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model
Y Shang, C Zhang, H Yu, CS Tan, X Zhao, SK Lim
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 693-698, 2013
372013
Robust clock tree synthesis with timing yield optimization for 3D-ICs
JS Yang, J Pak, X Zhao, SK Lim, DZ Pan
16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 621-626, 2011
352011
Variation-aware clock network design methodology for ultralow voltage (ULV) circuits
X Zhao, JR Tolbert, S Mukhopadhyay, SK Lim
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
222012
Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores
DL Lewis, S Panth, X Zhao, SK Lim, HHS Lee
2011 IEEE 29th International Conference on Computer Design (ICCD), 90-95, 2011
222011
Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores
DL Lewis, S Panth, X Zhao, SK Lim, HHS Lee
2011 IEEE 29th International Conference on Computer Design (ICCD), 90-95, 2011
222011
Analysis and design of energy and slew aware subthreshold clock systems
JR Tolbert, X Zhao, SK Lim, S Mukhopadhyay
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011
192011
Variation-tolerant and low-power clock network design for 3D ICs
X Zhao, S Mukhopadhyay, SK Lim
2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 2007-2014, 2011
192011
Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs
X Zhao, M Scheuermann, SK Lim
Proceedings of the 49th Annual Design Automation Conference, 157-162, 2012
182012
Buffered clock tree sizing for skew minimization under power and thermal budgets
K Athikulwongse, X Zhao, SK Lim
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 474-479, 2010
182010
An MTCMOS technology for low-power physical design
Q Zhou, X Zhao, Y Cai, X Hong
Integration 42 (3), 340-345, 2009
172009
Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs
X Zhao, SK Lim
17th Asia and South Pacific Design Automation Conference, 347-352, 2012
152012
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Artikelen 1–20