Helmut Puchner
Helmut Puchner
Cypress Semiconductor
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Investigation of multi-bit upsets in a 150 nm technology SRAM device
D Radaelli, H Puchner, S Wong, S Daniel
IEEE Transactions on Nuclear Science 52 (6), 2433-2437, 2005
SER--history, Trends and Challenges: A Guide for Designing with Memory ICs
JF Ziegler, H Puchner
Cypress, 2004
Silicon carbide CMOS channel
H Puchner
US Patent 6,358,806, 2002
Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for …
S Aronowitz, H Puchner, RA Kapre, JP Kimball
US Patent 6,331,468, 2001
Silicon germanium CMOS channel
H Puchner, GK Giust
US Patent 6,544,854, 2003
The contribution of low-energy protons to the total on-orbit SEU rate
NA Dodds, MJ Martinez, PE Dodd, MR Shaneyfelt, FW Sexton, JD Black, ...
IEEE Transactions on Nuclear Science 62 (6), 2440-2451, 2015
Dual nitrogen implantation techniques for oxynitride formation in semiconductor devices
SF Huang, H Puchner
US Patent 6,323,106, 2001
Isolation trench in semiconductor substrate with nitrogen-containing barrier region, and process for forming same
H Puchner, SF Huang, S Aronowitz
US Patent 6,156,620, 2000
Multiple cell upset classification in commercial SRAMs
G Tsiligiannis, L Dilillo, A Bosio, P Girard, S Pravossoudovitch, A Todri, ...
IEEE Transactions on Nuclear Science 61 (4), 1747-1754, 2014
Alpha-particle SEU performance of SRAM with triple well
H Puchner, D Radaelli, A Chatila
IEEE transactions on nuclear science 51 (6), 3525-3528, 2004
Elimination of single event latchup in 90nm SRAM technologies
H Puchner, R Kapre, S Sharifzadeh, J Majjiga, R Chao, D Radaelli, ...
2006 IEEE International Reliability Physics Symposium Proceedings, 721-722, 2006
Process for forming thin gate oxide with enhanced reliability by nitridation of upper surface of gate of oxide to form barrier of nitrogen atoms in upper surface region of gate …
S Aronowitz, J Haywood, JP Kimball, H Puchner, RM Kapre, N Eib
US Patent 6,413,881, 2002
Process impact on SRAM alpha-particle SEU performance
YZ Xu, H Puchner, A Chatila, O Pohland, B Bruggeman, B Jin, D Radaelli, ...
2004 IEEE International Reliability Physics Symposium. Proceedings, 294-299, 2004
SONOS type stacks for nonvolatile change trap memory devices and methods to form the same
H Puchner, I Polishchuk, S Levy
US Patent 8,163,660, 2012
NBTI reliability analysis for a 90 nm CMOS technology
H Puchner, L Hinh
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat …, 2004
JF Ziegler, H Puchner
Trends, and Challenges: A Guide for Designing with Memory ICs, 2004
High-voltage CMOS ESD and the safe operating area
AJ Walker, H Puchner, SP Dhanraj
IEEE Transactions on Electron Devices 56 (8), 1753-1760, 2009
SRAM variability and supply voltage scaling challenges
R Kapre, K Shakeri, H Puchner, J Tandigan, T Nigam, K Jang, ...
2007 IEEE International Reliability Physics Symposium Proceedings. 45th …, 2007
Well formation For CMOS devices integrated circuit structures
H Puchner, SF Huang, R Castagnetti
US Patent 6,144,076, 2000
Dynamic test methods for COTS SRAMs
G Tsiligiannis, L Dilillo, V Gupta, A Bosio, P Girard, A Virazel, H Puchner, ...
IEEE Transactions on Nuclear Science 61 (6), 3095-3102, 2014
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