Elham Cheshmikhani
TitelGeciteerd doorJaar
Investigating the effects of process variations and system workloads on reliability of STT-RAM caches
E Cheshmikhani, AMH Monazzah, H Farbeh, SG Miremadi
2016 12th European Dependable Computing Conference (EDCC), 120-129, 2016
112016
TA-LRW: A replacement policy for error rate reduction in STT-MRAM caches
E Cheshmikhani, H Farbeh, SG Miremadi, H Asadi
IEEE Transactions on Computers 68 (3), 455-470, 2018
92018
Probabilistic analysis of dynamic and temporal fault trees using accurate stochastic logic gates
E Cheshmikhani, HR Zarandi
Microelectronics Reliability 55 (11), 2468-2480, 2015
92015
Fast fault tree analysis for hybrid uncertainties using stochastic logic implemented on field‐programmable gate arrays: An application in quantitative assessment and mitigation …
S Shoar, HR Zarandi, F Nasirzadeh, E Cheshmikhani
Quality and Reliability Engineering International 33 (7), 1367-1385, 2017
82017
Enhancing reliability of STT-MRAM caches by eliminating read disturbance accumulation
E Cheshmikhani, H Farbeh, H Asadi
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 854-859, 2019
42019
ROBIN: Incremental Oblique Interleaved ECC for Reliability Improvement in STT-MRAM Caches
E Cheshmikhani, H Farbeh, H Asadi
IEEE 24th Asia and South Pacific Design Automation Conference (ASP-DAC), 173-178, 2019
42019
A-cache: alternating cache allocation to conduct higher endurance in NVM-based caches
H Farbeh, AMH Monazzah, E Aliagha, E Cheshmikhani
IEEE Transactions on Circuits and Systems II: Express Briefs 66 (7), 1237-1241, 2018
42018
Accelerating accurate fault tree analysis using HW/SW co-design
E Cheshmikhani, HR Zarandi, H Aliee
2014 Reliability and Maintainability Symposium, 1-6, 2014
42014
STAIR: HIGH RELIABLE STT-MRAM AWARE MULTI-LEVEL I/O CACHE ARCHITECTURE BY ADAPTIVE ECC ALLOCATION
M Hadizadeh, E Cheshmikhani, H Asadi
Design, Automation and Test in Europe Conference (DATE), 2020
2020
A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches
E Cheshmikhani, H Farbeh, H Asadi
IEEE Transactions on Reliability, 2019
2019
Preventing Read Disturbance Accumulation in STT-MRAM Caches
H Asadi, E Cheshmikhani, H Farbeh
US Patent App. App. No. 62809644,, 2019
2019
Accelerating Dynamic Fault Tree Analysis Based on Stochastic Logic Utilizing GPGPUs
E Cheshmikhani, HR Zarandi
2016 24th Euromicro International Conference on Parallel, Distributed, and …, 2016
2016
Het systeem kan de bewerking nu niet uitvoeren. Probeer het later opnieuw.
Artikelen 1–12