Ravi Pillarisetty
Ravi Pillarisetty
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Academic and industry research progress in germanium nanodevices
R Pillarisetty
Nature 479 (7373), 324-328, 2011
Non-planar gate all-around device and method of fabrication thereof
W Rachmady, R Pillarisetty, VH Le, JT Kavalieros, RS Chau, JS Kachian
US Patent 8,987,794, 2015
Fabrication, characterization, and physics of III–V heterojunction tunneling field effect transistors (H-TFET) for steep sub-threshold swing
G Dewey, B Chu-Kung, J Boardman, JM Fastenau, J Kavalieros, R Kotlyar, ...
2011 International electron devices meeting, 33.6. 1-33.6. 4, 2011
Methods of forming nickel sulfide film on a semiconductor device
SB Clendenning, N Mukherjee, R Pillarisetty
US Patent 7,964,490, 2011
Qubits made by advanced semiconductor manufacturing
AMJ Zwerver, T Krähenmann, TF Watson, L Lampert, HC George, ...
Nature Electronics 5 (3), 184-190, 2022
Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gate-to …
M Radosavljevic, G Dewey, D Basu, J Boardman, B Chu-Kung, ...
2011 international electron devices meeting, 33.1. 1-33.1. 4, 2011
CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
M Radosavljevic, R Pillarisetty, G Dewey, N Mukherjee, J Kavalieros, ...
US Patent 9,123,567, 2015
High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc= 0.5 V) III–V CMOS architecture
R Pillarisetty, B Chu-Kung, S Corcoran, G Dewey, J Kavalieros, H Kennel, ...
2010 International Electron Devices Meeting, 6.7. 1-6.7. 4, 2010
Unity beta ratio tri-gate transistor static random access memory (SRAM)
R Pillarisetty, S Datta, J Kavalieros, BS Doyle, U Shah
US Patent 7,825,437, 2010
Non-planar, multi-gate InGaAs quantum well field effect transistors with high-k gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic …
M Radosavljevic, G Dewey, JM Fastenau, J Kavalieros, R Kotlyar, ...
2010 International Electron Devices Meeting, 6.1. 1-6.1. 4, 2010
Transistors with high concentration of boron doped germanium
AS Murthy, GA Glass, T Ghani, R Pillarisetty, N Mukherjee, JT Kavalieros, ...
US Patent 8,901,537, 2014
High-performance 40nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (VCC= 0.5 V) logic applications
M Radosavljevic, T Ashley, A Andreev, SD Coomber, G Dewey, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
Techniques for forming shallow trench isolation
W Rachmady, BY Jin, R Pillarisetty, RS Chau
US Patent App. 12/639,451, 2011
Variable gate width for gate all-around transistors
W Rachmady, VH Le, R Pillarisetty, JT Kavalieros, RS Chau, SH Sung
US Patent 9,590,089, 2017
Non-planar germanium quantum well devices
R Pillarisetty, JT Kavalieros, W Rachmady, U Shah, B Chu-Kung, ...
US Patent 8,283,653, 2012
Group III-V devices with delta-doped layer under channel region
MK Hudait, PG Tolchinsky, RS Chau, M Radosavljevic, R Pillarisetty, ...
US Patent App. 12/316,878, 2010
Non-planar quantum well device having interfacial layer and method of forming same
W Rachmady, R Pillarisetty, VH Le, R Chau
US Patent 8,575,653, 2013
Heterogeneous integration of enhancement mode in0.7ga0.3as quantum well transistor on silicon substrate using thin (les 2 μm) composite buffer architecture for …
MK Hudait, G Dewey, S Datta, JM Fastenau, J Kavalieros, WK Liu, ...
2007 IEEE International Electron Devices Meeting, 625-628, 2007
Modulation-doped multi-gate devices
MK Hudait, R Pillarisetty, M Radosavljevic, G Dewey, JT Kavalieros
US Patent 8,120,063, 2012
Carrier transport in high-mobility III–V quantum-well transistors and performance impact for high-speed low-power logic applications
G Dewey, MK Hudait, K Lee, R Pillarisetty, W Rachmady, M Radosavljevic, ...
IEEE electron device letters 29 (10), 1094-1097, 2008
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