Davor Capalija
Davor Capalija
Tenstorrent Inc.
Verified email at mail.utoronto.ca
Cited by
Cited by
An opencl™ deep learning accelerator on arria 10
U Aydonat, S O'Connell, D Capalija, AC Ling, GR Chiu
Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017
A multithreaded soft processor for SoPC area reduction
B Fort, D Capalija, ZG Vranesic, SD Brown
2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing …, 2006
A high-performance overlay architecture for pipelined execution of data flow graphs
D Capalija, TS Abdelrahman
2013 23rd International Conference on Field programmable Logic and …, 2013
Microarchitecture of a coarse-grain out-of-order superscalar processor
D Capalija, TS Abdelrahman
IEEE Transactions on Parallel and Distributed Systems 24 (2), 392-405, 2012
Towards synthesis-free JIT compilation to commodity FPGAs
D Capalija, TS Abdelrahman
2011 IEEE 19th Annual International Symposium on Field-Programmable Custom …, 2011
Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays
D Capalija, TS Abdelrahman
2014 24th International Conference on Field Programmable Logic and …, 2014
In-package domain-specific asics for intel® stratix® 10 fpgas: A case study of accelerating deep learning using tensortile asic
E Nurvitadhi, J Cook, A Mishra, D Marr, K Nealis, P Colangelo, A Ling, ...
2018 28th International Conference on Field Programmable Logic and …, 2018
Coopetition mechanisms for service-oriented distributed systems
A Milanović, S Srbljić, D Skrobo, D Čapalija, S Rešković
Proceedings of the 3rd International Conference on Computing, Communication …, 2005
The MLCA: a solution paradigm for parallel programmable SoCs
T Abdelrahman, A Abdelkhalek, U Aydonat, D Capalija, D Han, ...
IEEE North-East Workshop on Circuits and Systems (NEWCAS), 253-253, 2006
Memory-Size-and Bandwidth-Efficient Method for Feeding Systolic Array Matrix Multipliers
JZ Yinger, A Ling, T Czajkowski, D Capalija, E Nurvitadhi, D Marr
US Patent App. 15/644,526, 2019
Customizable FPGA OpenCL matrix multiply design template for deep neural networks
J Yinger, E Nurvitadhi, D Capalija, A Ling, D Marr, S Krishnan, D Moss, ...
2017 International Conference on Field Programmable Technology (ICFPT), 259-262, 2017
Method and Apparatus for Performing Different Types of Convolution Operations with the Same Processing Elements
M Lele, D Capalija, AC Ling
US Patent App. 15/367,101, 2018
A coarse-grain fpga overlay for executing data flow graphs
D Capalija, T Abdelrahman
The Second Workshop on the Intersections of Computer Architecture and …, 2012
An architecture for exploiting coarse-grain parallelism on FPGAs
D Capalija, TS Abdelrahman
2009 International Conference on Field-Programmable Technology, 285-291, 2009
Flexibility: Fpgas and cad in deep learning acceleration
GR Chiu, AC Ling, D Capalija, A Bitar, MS Abdelfattah
Proceedings of the 2018 International Symposium on Physical Design, 34-41, 2018
Creating High Performance Applications with Intel's FPGA OpenCL™ SDK
AC Ling, U Aydonat, S O'Connell, D Capalija, GR Chiu
Proceedings of the 5th International Workshop on OpenCL, 1-1, 2017
Objava-pretplata mehanizmi za ostvarivanje mreža zasnovanih na sadržaju
D Čapalija
diplomski rad, Fakultet elektrotehnike i računarstva, Sveučilište u Zagrebu …, 2005
Microarchitecture and FPGA implementation of the multi-level computing architecture
D Capalija
Dot product based processing elements
AC Ling, D Capalija, TS Czajkowski, AMH Miriste
US Patent 10,049,082, 2018
An OpenCL (TM) Deep Learning Accelerator on Arria
U Aydonat, S O'Connell, D Capalija, AC Ling, GR Chiu
Field-Programmable Gate Arrays 10, 2017
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