Ian A Young
Cited by
Cited by
A PLL clock generator with 5 to 110 MHz of lock range for microprocessors
IA Young, JK Greason, KL Wong
IEEE Journal of Solid-State Circuits 27 (11), 1599-1607, 1992
Overview of beyond-CMOS devices and a uniform methodology for their benchmarking
DE Nikonov, IA Young
Proceedings of the IEEE 101 (12), 2498-2533, 2013
Optical I/O technology for tera-scale computing
IA Young, E Mohammed, JTS Liao, AM Kern, S Palermo, BA Block, ...
IEEE Journal of solid-state circuits 45 (1), 235-248, 2009
Tunnel field-effect transistors: Prospects and challenges
UE Avci, DH Morris, IA Young
IEEE Journal of the Electron Devices Society 3 (3), 88-95, 2015
On-Chip Optical Interconnects.
MJ Kobrinsky, BA Block, JF Zheng, BC Barnett, E Mohammed, ...
Intel Technology Journal 8 (2), 2004
Benchmarking of beyond-CMOS exploratory devices for logic integrated circuits
DE Nikonov, IA Young
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 1 …, 2015
Clock generation and distribution for the first IA-64 microprocessor
S Tam, S Rusu, UN Desai, R Kim, J Zhang, I Young
IEEE Journal of Solid-State Circuits 35 (11), 1545-1552, 2000
Scalable energy-efficient magnetoelectric spin–orbit logic
S Manipatruni, DE Nikonov, CC Lin, TA Gosavi, H Liu, B Prasad, ...
Nature 565 (7737), 35, 2019
Clock distribution network
MJ Paniccia, IA Young, TP Thomas, VRM Rao
US Patent 6,125,217, 2000
Beyond CMOS computing with spin and polarization
S Manipatruni, DE Nikonov, IA Young
Nature Physics 14 (4), 338-343, 2018
Optical interconnect system integration for ultra-short-reach applications
E Mohammed, A Alduino, T Thomas, H Braunisch, D Lu, J Heck, A Liu, ...
Intel Technology Journal 8 (2), 115-127, 2004
CMOS scaling trends and beyond
MT Bohr, IA Young
IEEE Micro 37 (6), 20-29, 2017
Comparison of performance, switching energy and process variations for the TFET and MOSFET in logic
UE Avci, R Rios, K Kuhn, IA Young
2011 Symposium on VLSI Technology-Digest of Technical Papers, 124-125, 2011
Mechanisms of interface trap-induced drain leakage current in off-state n-MOSFET's
TE Chang, C Huang, T Wang
IEEE Transactions on electron devices 42 (4), 738-743, 1995
Flip-chip package integrating optical and electrical devices and coupling to a waveguide on a board
KK Chakravorty, J Swan, BC Barnett, JF Ahadian, TP Thomas, I Young
US Patent 6,754,407, 2004
MOS switched-capacitor analog sampled-data direct-form recursive filters
IA Young, DA Hodges
IEEE Journal of Solid-State Circuits 14 (6), 1020-1033, 1979
Coupled-oscillator associative memory array operation for pattern recognition
DE Nikonov, G Csaba, W Porod, T Shibata, D Voils, D Hammerstrom, ...
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 1 …, 2015
Scaled TFET transistor formed using nanowire with surface termination
UE Avci, R Rios, KJ Kuhn, IA Young, JR Weber
US Patent 10,535,770, 2020
Dual Threshold Voltages and Substrate Bias: Keys to High Performance, Low Power, 0.1 m Logic Designs
S Thompson, I Young, J Greason, M Bohr
Symposium on VLSI Technology, 69-70, 1997
Current probe device having an integrated amplifier
TP Thomas, DN Stunkard, MR Reshotko, BC Barnett, IA Young
US Patent 6,856,129, 2005
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