| Delay insensitive encoding and power analysis: a balancing act [cryptographic hardware protection] KJ Kulikowski, M Su, A Smirnov, A Taubin, MG Karpovsky, D MacDonald Asynchronous Circuits and Systems, 2005. ASYNC 2005. Proceedings. 11th IEEE …, 2005 | 61 | 2005 |
| Automated design of cryptographic devices resistant to multiple side-channel attacks K Kulikowski, A Smirnov, A Taubin Cryptographic Hardware and Embedded Systems-CHES 2006: 8th International …, 2006 | 34 | 2006 |
| An automated fine-grain pipelining using domino style asynchronous library A Smirnov, A Taubin, M Su, M Karpovsky Fifth International Conference on Application of Concurrency to System …, 2005 | 28 | 2005 |
| Heuristic based throughput analysis and optimization of asynchronous pipelines A Smirnov, A Taubin 2009 15th IEEE Symposium on Asynchronous Circuits and Systems, 162-172, 2009 | 20 | 2009 |
| Towards synthesis of monotonic asynchronous circuits from signal transition graphs N Starodoubtsev, S Bystrov, M Goncharov, I Klotchkov, A Smirnov Application of Concurrency to System Design, 2001. Proceedings. 2001 …, 2001 | 19 | 2001 |
| Synthesizing asynchronous micropipelines with design compiler A Smirnov, A Taubin Synopsys Users Group, 2006 | 13 | 2006 |
| Gate transfer level synthesis as an automated approach to fine-grain pipelining A Smirnov, A Taubin, M Karpovsky, L Rozenblyum Workshop on Token Based Computing (ToBaCo), 67-77, 2004 | 13 | 2004 |
| Automated pipelining in ASIC synthesis methodology: Gate transfer level A Smirnov, A Taubin, M Karpovsky IWLS 2004 thirteenth international workshop on logic and synthesis, 2-4, 2004 | 7 | 2004 |
| Asynchronous micropipeline synthesis system AB Smirnov ProQuest, 2009 | 5 | 2009 |
| A case study for the verification of complex timed circuits: IPCMOS MA Pena, J Cortadella, E Pastor, A Smirnov Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002 | 5 | 2002 |
| Synthesis of asynchronous interface circuits by STG refinement N Starodoubtsev, M Goncharov, I Klotchkov, A Smirnov Asynchronous Interfaces: Tools, Techniques, and Implementations, 65-74, 2000 | 5 | 2000 |
| Timing extensions of STG model and a method to simulate timed STG behavior in VHDL environment MV Goncharov, AB Smirnov, IV Klotchkov, NA Starodoubtsev Proceedings 1998 International Conference on Application of Concurrency to …, 1998 | 3 | 1998 |
| Timing extensions of STG model and a method to simulate timed STG behavior in VHDL environment MV Goncharov, AB Smirnov, IV Klotchkov, NA Starodoubtsev Proceedings 1998 International Conference on Application of Concurrency to …, 1998 | 3 | 1998 |
| STG refinement for synthesis of negative gates' circuits M Goncharov, I Klotchkov, E Klypkin, A Smirnov, N Starodoubtsev Handouts of the AciD-WG Workshop, Univ. of Newcastle upon Tyne, Tech. report …, 1999 | 2 | 1999 |
| Verification driven synthesis of asynchronous circuits from STG specification IV Klotchkov, AB Smirnov, NA Starodoubtsev Power and Timing Modeling, Optimization and Simulation (PATMOS), 377-386, 1998 | 2 | 1998 |
| Stg timing extensions and simulation MV Goncharov, AB Smirnov, IV Klotchkov, NA Starodoubtsev Proceedings International Verilog HDL Conference and VHDL International …, 1998 | 1 | 1998 |
| STG timing extensions and simulation MV Goncharov, AB Smirnov, IV Klotchkov, NA Starodoubtsev Proceedings International Verilog HDL Conference and VHDL International …, 1998 | 1 | 1998 |
| A technique to automate STG analysis and refinement for CSC and normalcy A Smirnov, M Goncharov, I Klotchkov, N Starodoubtsev | | 2001 |
| Formal verification of a complex timed circuit: IPCMOS MA Pena, J Cortadella, E Pastor, A Smirnov | | |
Mark G. KarpovskyProfessor of Computer Engineering, Boston UniversityGeverifieerd e-mailadres voor bu.edu
