Guido Masera
Guido Masera
Professor of Electronics, Politecnico di Torino
Verified email at polito.it
Title
Cited by
Cited by
Year
VLSI architectures for turbo codes
G Masera, G Piccinini, MR Roch, M Zamboni
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7 (3), 369-379, 1999
2131999
Implementation of a flexible LDPC decoder
G Masera, F Quaglio, F Vacca
IEEE Transactions on Circuits and Systems II: Express Briefs 54 (6), 542-546, 2007
1482007
Multiplierless, folded 9/7–5/3 wavelet VLSI architecture
M Martina, G Masera
IEEE Transactions on Circuits and Systems II: Express Briefs 54 (9), 770-774, 2007
892007
Architectural strategies for low-power VLSI turbo decoders
G Masera, M Mazza, G Piccinini, F Viglione, M Zamboni
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10 (3), 279-285, 2002
652002
VLSI implementation of a multi-mode turbo/LDPC decoder architecture
C Condo, M Martina, G Masera
IEEE Transactions on Circuits and Systems I: Regular Papers 60 (6), 1441-1454, 2012
642012
High speed architectures for finding the first two maximum/minimum values
LG Amarù, M Martina, G Masera
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (12 …, 2011
562011
Low-complexity, efficient 9/7 wavelet filters VLSI implementation
M Martina, G Masera
IEEE Transactions on Circuits and Systems II: Express Briefs 53 (11), 1289-1293, 2006
552006
On optimal and near-optimal turbo decoding using generalized max operator
S Papaharalabos, PT Mathiopoulos, G Masera, M Martina
IEEE Communications Letters 13 (7), 522-524, 2009
542009
A VLSI architecture for IWT (integer wavelet transform)
M Martina, G Masera, G Piccinini, M Zamboni
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat …, 2000
512000
Quantum dot cellular automata check node implementation for LDPC decoders
M Awais, M Vacca, M Graziano, MR Roch, G Masera
IEEE transactions on nanotechnology 12 (3), 368-377, 2013
492013
Motion estimation and CABAC VLSI co-processors for real-time high-quality H. 264/AVC video coding
S Saponara, M Martina, M Casula, L Fanucci, G Masera
Microprocessors and Microsystems 34 (7-8), 316-328, 2010
432010
Finite precision implementation of LDPC decoders
G Masera, F Quaglio, F Vacca
IEE Proceedings-Communications 152 (6), 1098-1102, 2005
432005
A flexible UMTS-WiMax turbo decoder architecture
M Martina, M Nicola, G Masera
IEEE Transactions on Circuits and Systems II: Express Briefs 55 (4), 369-373, 2008
422008
Turbo NOC: A framework for the design of network-on-chip-based turbo decoder architectures
M Martina, G Masera
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (10), 2776-2789, 2010
402010
Resource management for software-defined radio clouds
I Gomez, V Marojevic, A Gelonch
IEEE micro 32 (1), 44-53, 2011
362011
Interconnection framework for high-throughput, flexible LDPC decoders
F Quaglio, F Vacca, C Castellano, A Tarable, G Masera
Proceedings of the Design Automation & Test in Europe Conference 2, 6 pp., 2006
352006
Adaptive approximated DCT architectures for HEVC
M Masera, M Martina, G Masera
IEEE Transactions on Circuits and Systems for Video Technology 27 (12), 2714 …, 2016
322016
Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations
M Martina, G Masera, G Piccinini, M Zamboni
Journal of VLSI signal processing systems for signal, image and video …, 2003
312003
An LDPC decoder architecture for wireless sensor network applications
ADG Biroli, M Martina, G Masera
Sensors 12 (2), 1529-1543, 2012
282012
A network-on-chip-based turbo/LDPC decoder architecture
C Condo, M Martina, G Masera
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012
272012
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