| BAG2: A process-portable framework for generator-based AMS circuit design E Chang, J Han, W Bae, Z Wang, N Narevsky, B Nikolic, E Alon 2018 IEEE Custom Integrated Circuits Conference (CICC), 1-8, 2018 | 134 | 2018 |
| A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET J Im, D Freitas, A Bantug Roldan, R Casey, S Chen, CH Adam Chou, ... IEEE Journal of Solid-State Circuits 52 (12), 3486-3502, 2017 | 115 | 2017 |
| 6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET J Im, D Freitas, A Bantug Roldan, R Casey, S Chen, CH Adam Chou, ... Solid-State Circuits Conference (ISSCC), 2017 IEEE International, 114-115, 2017 | 115* | 2017 |
| Cable connector retaining assembly, system, and method of assembling same MG Clark, RC Laning, CM Marroquin, BJ Stanczyk, RV Tointon US Patent 6,964,578, 2005 | 51 | 2005 |
| Design techniques for a 60-Gb/s 288-mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65-nm CMOS technology J Han, N Sutardja, Y Lu, E Alon IEEE Journal of Solid-State Circuits 52 (12), 3474-3485, 2017 | 40 | 2017 |
| Design techniques for a 60 Gb/s 173 mW wireline receiver frontend in 65 nm CMOS technology J Han, Y Lu, N Sutardja, K Jung, E Alon IEEE Journal of Solid-State Circuits 51 (4), 871-880, 2016 | 38 | 2016 |
| LAYGO: A template-and-grid-based layout generation engine for advanced CMOS technologies J Han, W Bae, E Chang, Z Wang, B Nikolić, E Alon IEEE Transactions on Circuits and Systems I: Regular Papers 68 (3), 1012-1022, 2021 | 32 | 2021 |
| A 4.8 Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface WY Shin, GM Hong, H Lee, JD Han, S Kim, KS Park, DH Lim, JH Chun, ... 2011 IEEE International Solid-State Circuits Conference, 494-496, 2011 | 32 | 2011 |
| 6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology J Han, Y Lu, N Sutardja, E Alon 2017 IEEE International Solid-State Circuits Conference (ISSCC), 112-113, 2017 | 28 | 2017 |
| 8 An output-bandwidth-optimized 200Gb/s PAM-4 100Gb/s NRZ transmitter with 5-Tap FFE in 28nm CMOS M Choi, Z Wang, K Lee, K Park, Z Liu, A Biswas, J Han, E Alon 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 128-130, 2021 | 27 | 2021 |
| An output bandwidth optimized 200-Gb/s PAM-4 100-Gb/s NRZ transmitter with 5-tap FFE in 28-nm CMOS Z Wang, M Choi, K Lee, K Park, Z Liu, A Biswas, J Han, S Du, E Alon IEEE Journal of Solid-State Circuits 57 (1), 21-31, 2021 | 21 | 2021 |
| A 60Gb/s 173mW receiver frontend in 65nm CMOS technology J Han, Y Lu, N Sutardja, K Jung, E Alon 2015 Symposium on VLSI Circuits (VLSI Circuits), C230-C231, 2015 | 18 | 2015 |
| A mixed-signal risc-v signal analysis soc generator with a 16-nm finfet instance S Bailey, P Rigge, J Han, R Lin, EY Chang, H Mao, Z Wang, C Markley, ... IEEE Journal of Solid-State Circuits 54 (10), 2786-2801, 2019 | 15 | 2019 |
| A supply-scalable-serializing transmitter with controllable output swing and equalization for next-generation standards W Bae, H Ju, K Park, J Han, DK Jeong IEEE Transactions on Industrial Electronics 65 (7), 5979-5989, 2017 | 15 | 2017 |
| A real-time, 1.89-GHz bandwidth, 175-kHz resolution sparse spectral analysis RISC-V SoC in 16-nm FinFET A Wang, W Bae, J Han, S Bailey, O Ocal, P Rigge, Z Wang, ... IEEE Journal of Solid-State Circuits 54 (7), 1993-2008, 2019 | 11 | 2019 |
| An automated SerDes frontend generator verified with a 16-nm instance achieving 15 Gb/s at 1.96 pJ/bit E Chang, N Narevsky, J Han, E Alon IEEE Solid-State Circuits Letters 1 (12), 245-248, 2018 | 11 | 2018 |
| 4-slot, 8-drop impedance-matched bidirectional multidrop DQ bus with a 4.8-Gb/s memory controller transceiver WY Shin, GM Hong, H Lee, JD Han, KS Park, DH Lim, S Kim, D Shim, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 3 (5 …, 2013 | 11 | 2013 |
| A generated 7GS/s 8b time-interleaved SAR ADC with 38.2 dB SNDR at Nyquist in 16nm CMOS FinFET J Han, E Chang, S Bailey, Z Wang, W Bae, A Wang, N Narevsky, ... 2019 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2019 | 8 | 2019 |
| A generated multirate signal analysis RISC-V SoC in 16nm FinFET S Bailey, J Han, P Rigge, R Lin, E Chang, H Mao, Z Wang, C Markley, ... 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 285-288, 2018 | 7 | 2018 |
| A real-time, analog/digital co-designed 1.89-GHz bandwidth, 175-kHz resolution sparse spectral analysis RISC-V SoC in 16-nm FinFET A Wang, W Bae, J Han, S Bailey, P Rigge, O Ocal, Z Wang, ... ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC …, 2018 | 6 | 2018 |
Woorham BaeAyar Labs, Santa ClaraGeverifieerd e-mailadres voor ayarlabs.com
