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Ramin Rajaei, Ph.D.
Ramin Rajaei, Ph.D.
Senior FPGA Design Engineer at Jariet Technologies, Inc
Geverifieerd e-mailadres voor jariettech.com - Homepage
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Design of Robust SRAM Cells Against Single-Event Multiple Effects for Nanometer Technologies
R Rajaei, B Asgari, M Tabandeh, M Fazeli
IEEE Transactions on Device and Materials Reliability 15 (3), 429 - 436, 2015
852015
Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation
R Rajaei, M Tabandeh, M Fazeli
Microelectronics Reliability 53 (6), 912-924, 2013
662013
Fully Nonvolatile and Low Power Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction with Spin-Hall Effect Assistance
A Amirany, R Rajaei
IEEE Transactions on Magnetics, 2018
562018
Single event multiple upset (SEMU) tolerant latch designs in presence of process and temperature variations
R Rajaei, M Tabandeh, M Fazeli
Journal of Circuits, Systems and Computers 24 (01), 1550007, 2015
562015
Radiation Hardened Design of Nonvolatile MRAM-based FPGA
R Rajaei
IEEE Transactions on Magnetics (TMAG), 2016
552016
A Variation-Aware Ternary Spin-Hall Assisted STT-RAM Based on Hybrid MTJ/GAA-CNTFET Logic
F Razi, MH Moaiyeri, R Rajaei, S Mohammadi
IEEE Transactions on Nanotechnology, 2019
502019
Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design
R Rajaei, S Bakhtavari Mamaghani
IEEE Transactions on Device and Materials Reliability (TDMR), 2017
462017
In-Memory Nearest Neighbor Search with FeFET Multi-Bit Content-Addressable Memories
A Kazemi, MM Sharifi, AF Laguna, F Müller, R Rajaei, R Olivo, T Kämpfe, ...
Design, Automation and Test in Europe Conference (DATE'21), 2021
402021
A novel hybrid algorithm for creating self-organizing fuzzy neural networks
O Khayat, MM Ebadzadeh, HR Shahdoosti, R Rajaei, I Khajehnasiri
Neurocomputing 73 (1-3), 517-524, 2009
392009
Nonvolatile, Spin-Based, and Low-Power Inexact Full Adder Circuits for Computing-in-Memory Image Processing
A Amirany, R Rajaei
SPIN, 2019
372019
Single event upset immune latch circuit design using C-element
R Rajaei, M Tabandeh, B Rashidian
2011 9th IEEE International Conference on ASIC, 252-255, 2011
342011
In-memory computing with associative memories: A cross-layer perspective
XS Hu, M Niemier, A Kazemi, AF Laguna, K Ni, R Rajaei, MM Sharifi, ...
2021 IEEE International Electron Devices Meeting (IEDM), 25.2. 1-25.2. 4, 2021
322021
Nonvolatile Low-Cost Approximate Spintronic Full-Adders for Computing-in-Memory Architectures
R Rajaei, A Amirany
IEEE Transactions on Magnetics, 2020
322020
Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology
R Rajaei, B Asgari, M Tabandeh, M Fazeli
Turkish Journal of Electrical Engineering & Computer Sciences, 2016
322016
Nonvolatile Spin-Based Radiation Hardened Retention Latch and Flip-Flop
A Amirany, F Marvi, K Jafari, R Rajaei
IEEE Transactions on Nanotechnology, 2019
312019
Soft Error-Tolerant Design of MRAM-based Non-Volatile Latches for Sequential Logics
R Rajaei, M Fazeli, M Tabandeh
IEEE Transactions on Magnetics (TMAG) 51 (6), 2014
302014
A Low-Cost and Highly Reliable Spintronics True Random Number Generator Circuit for Secure Cryptography
I Alibeigi, A Amirany, R Rajaei, M Tabandeh, S Bagheri Shouraki
SPIN, 2019
262019
Compact Single-Phase-Search Multi-State Content Addressable Memory Design using 1 FeFET/Cell
R Rajaei, MM Sharifi, A Kazemi, M Niemier, XS Hu
IEEE Transaction on Electron Devices, 2021
252021
Single Event Double Node Upset Tolerance in MOS/Spintronic Sequential and Combinational Logic Circuits
R Rajaei
Microelectronics Reliability (MR), 2017
252017
Spin-based Fully Nonvolatile Full-Adder Circuit for Computing in Memory
A Amirany, R Rajaei
SPIN, 2019
242019
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Artikelen 1–20