| Innovative materials, devices, and CMOS technologies for low-power mobile multimedia T Skotnicki, C Fenouillet-Beranger, C Gallon, F Boeuf, S Monfray, F Payet, ... IEEE transactions on electron devices 55 (1), 96-130, 2007 | 269 | 2007 |
| A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications F Boeuf, S Crémer, N Vulliet, T Pinguet, A Mekis, G Masini, L Verslegers, ... 2013 IEEE International Electron Devices Meeting, 13.3. 1-13.3. 4, 2013 | 121 | 2013 |
| Reliable 300 mm wafer level hybrid bonding for 3D stacked CMOS image sensors S Lhostis, A Farcy, E Deloffre, F Lorut, S Mermoz, Y Henrion, L Berthier, ... 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 869-876, 2016 | 108 | 2016 |
| High frequency characterization and modeling of high density TSV in 3D integrated circuits C Bermond, L Cadix, A Farcy, T Lacrevaz, P Leduc, B Flechet 2009 IEEE Workshop on Signal Propagation on Interconnects, 1-4, 2009 | 87 | 2009 |
| IntAct: A 96-core processor with six chiplets 3D-stacked on an active interposer with distributed interconnects and integrated power management P Vivet, E Guthmuller, Y Thonnart, G Pillonnet, C Fuguet, I Miro-Panades, ... IEEE Journal of Solid-State Circuits 56 (1), 79-97, 2020 | 86 | 2020 |
| Recent progress in silicon photonics R&D and manufacturing on 300mm wafer platform F Bœuf, S Cremer, E Temporiti, M Fere, M Shaw, N Vulliet, B Orlando, ... Optical Fiber Communication Conference, W3A. 1, 2015 | 85 | 2015 |
| Hybrid bonding for 3D stacked image sensors: impact of pitch shrinkage on interconnect robustness J Jourdon, S Lhostis, S Moreau, J Chossat, M Arnoux, C Sart, Y Henrion, ... 2018 IEEE International Electron Devices Meeting (IEDM), 7.3. 1-7.3. 4, 2018 | 75 | 2018 |
| Euroserver: Energy efficient node for european micro-servers Y Durand, PM Carpenter, S Adami, A Bilas, D Dutoit, A Farcy, ... 2014 17th Euromicro Conference on Digital System Design, 206-213, 2014 | 72 | 2014 |
| Investigation on TSV impact on 65nm CMOS devices and circuits H Chaabouni, M Rousseau, P Leduc, A Farcy, R El Farhane, A Thuaire, ... 2010 International Electron Devices Meeting, 35.1. 1-35.1. 4, 2010 | 68 | 2010 |
| 2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm … P Vivet, E Guthmuller, Y Thonnart, G Pillonnet, G Moritz, I Miro-Panadès, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 46-48, 2020 | 66 | 2020 |
| Active interposer technology for chiplet-based advanced 3D system architectures P Coudrain, J Charbonnier, A Garnier, P Vivet, R Vélard, A Vinci, ... 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 569-578, 2019 | 64 | 2019 |
| Modelling of through silicon via RF performance and impact on signal transmission in 3D integrated circuits L Cadix, A Farcy, C Bermond, C Fuchs, P Leduc, M Rousseau, M Assous, ... 2009 IEEE International Conference on 3D System Integration, 1-7, 2009 | 59 | 2009 |
| Sidewall restoration of porous ultra low-k dielectrics for sub-45 nm technology nodes H Chaabouni, LL Chapelon, M Aimadeddine, J Vitiello, A Farcy, R Delsol, ... Microelectronic Engineering 84 (11), 2595-2599, 2007 | 52 | 2007 |
| 1μm Pitch direct hybrid bonding with< 300nm wafer-to-wafer overlay accuracy A Jouve, V Balan, N Bresson, C Euvrard-Colnat, F Fournel, Y Exbrayat, ... 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2017 | 48 | 2017 |
| Semiconductor device comprising a capacitor and an electrical connection via, and fabrication method S Joblot, A Farcy, JF Carpentier, P Bar US Patent 8,841,749, 2014 | 48 | 2014 |
| Advanced Cu interconnects using air gaps LG Gosset, A Farcy, J De Pontcharra, P Lyan, R Daamen, G Verheijden, ... Microelectronic engineering 82 (3-4), 321-332, 2005 | 47 | 2005 |
| Devices and methods for treating and closing wounds with negative pressure AC Dagger, NC Fry, JK Hicks, EM Huddleston, MD Phillips, C Saxby, ... US Patent 10,117,782, 2018 | 42* | 2018 |
| RF characterization and modelling of high density through silicon vias for 3D chip stacking L Cadix, C Bermond, C Fuchs, A Farcy, P Leduc, L DiCioccio, M Assous, ... Microelectronic Engineering 87 (3), 491-495, 2010 | 42 | 2010 |
| An evaluation of the CMOS technology roadmap from the point of view of variability, interconnects, and power dissipation F Boeuf, M Sellier, A Farcy, T Skotnicki IEEE Transactions on Electron Devices 55 (6), 1433-1440, 2008 | 42 | 2008 |
| Integrated circuit comprising an auxiliary component, for example a passive component or a microelectromechanical system, placed above an electronic chip, and the corresponding … A Farcy, P Coronel, P Ancey, J Torres US Patent 6,846,690, 2005 | 41 | 2005 |
