| Design and implementation of a Viterbi decoder using FPGAs B Pandita, SK Roy Proceedings Twelfth International Conference on VLSI Design.(Cat. No …, 1999 | 55 | 1999 |
| Approximation algorithms for min-k-overlap problems using the principal lattice of partitions approach H Narayanan, S Roy, S Patkar Journal of Algorithms 21 (2), 306-330, 1996 | 28 | 1996 |
| Functional verification of system on chips-practices, issues and challenges SK Roy, S Ramesh Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design …, 2002 | 23 | 2002 |
| Functional verification of system on chips-practices, issues and challenges SK Roy, S Ramesh Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design …, 2002 | 23 | 2002 |
| Top level SOC interconnectivity verification using formal techniques SK Roy 2007 Eighth International Workshop on Microprocessor Test and Verification …, 2007 | 21 | 2007 |
| Optimization of tube hydroforming with consideration of manufacturing effects on structural performance D Kirby, S Roy, R Kunju AIP Conference Proceedings 778 (1), 585-590, 2005 | 11 | 2005 |
| TECHMIG: A layout tool for technology migration PK Kar, SK Roy Proceedings Twelfth International Conference on VLSI Design.(Cat. No …, 1999 | 10 | 1999 |
| A new methodology for the design of asynchronous digital circuits K Nanda, SK Desai, SK Roy Proceedings Tenth International Conference on VLSI Design, 342-347, 1997 | 10 | 1997 |
| Towards formal verification of analog mixed signal designs using SPICE circuit simulation traces K Lata, SK Roy, HS Jamadagni 2009 1st Asia Symposium on Quality Electronic Design, 162-172, 2009 | 9 | 2009 |
| Verification of a MEMS based adaptive cruise control system using simulation and semi-formal approaches S Jairam, K Lata, SK Roy, N Bhat 2008 15th IEEE International Conference on Electronics, Circuits and Systems …, 2008 | 9 | 2008 |
| Formal verification based on assume and guarantee approach—a case study (short paper) SK Roy, H Iwashita, T Nakata Proceedings of the 2000 Asia and South Pacific Design Automation Conference …, 2000 | 9 | 2000 |
| Accelerating the Activation Function Selection for Hybrid Deep Neural Networks–FPGA Implementation SM Waseem, AV Suraj, SK Roy 2021 IEEE Region 10 Symposium (TENSYMP), 1-7, 2021 | 6 | 2021 |
| An Automated and Flexible Approach to Optimal Design of Shape and Process Variables for Stamped Parts S Roy, R Kunju, D Kirby The Fifth International Conference and Workshop on Numerical Simulation of …, 2002 | 6 | 2002 |
| Min k-cut and the principal partition of a graph H Narayanan, S Roy, S Patkar Proceedings of Second National Seminar on Theoretical Computer Science …, 1992 | 6 | 1992 |
| Defeating hatch: Building malicious ip cores A Bhardwaj, SK Roy VLSI Design and Test: 21st International Symposium, VDAT 2017, Roorkee …, 2017 | 5 | 2017 |
| DFT logic verification through property based formal methods—SOC to IP L Sen, A Roy, S Bhattacharjee, B Mittra, SK Roy Formal Methods in Computer Aided Design, 33-33, 2010 | 5 | 2010 |
| Hardware realization of reinforcement learning algorithms for edge devices SM Waseem, SK Roy VLSI and Hardware Implementations Using Modern Machine Learning Methods, 233-254, 2021 | 4 | 2021 |
| Modeling techniques for formal verification of BIST controllers and their integration into SOC designs SK Roy, RA Parekhji 20th International Conference on VLSI Design held jointly with 6th …, 2007 | 4 | 2007 |
| An interactive and flexible approach to stamping design and optimization S Roy, R Kunju, D Kirby AIP Conference Proceedings 712 (2), 1975-1979, 2004 | 4 | 2004 |
| A new approach to the problem of PLA partitioning using the theory of the principal lattice of partitions of a submodular function S Roy, H Narayanan [1991] Proceedings Fourth Annual IEEE International ASIC Conference and …, 1991 | 4 | 1991 |
