Masoud Zamani
Masoud Zamani
Staff Engineer, Qualcomm Inc.
Geverifieerd e-mailadres voor qti.qualcomm.com
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Online fault testing of reversible logic using dual rail coding
N Farazmand, M Zamani, MB Tahoori
2010 IEEE 16th International On-Line Testing Symposium, 204-205, 2010
352010
ILP formulations for variation/defect-tolerant logic mapping on crossbar nano-architectures
M Zamani, H Mirzaei, MB Tahoori
ACM Journal on Emerging Technologies in Computing Systems (JETC) 9 (3), 1-21, 2013
172013
Fault masking and diagnosis in reversible circuits
M Zamani, N Farazmand, MB Tahoori
2011 sixteenth IEEE European test symposium, 69-74, 2011
172011
Ping-pong test: Compact test vector generation for reversible circuits
M Zamani, MB Tahoori, K Chakrabarty
2012 IEEE 30th VLSI Test Symposium (VTS), 164-169, 2012
162012
Variation-aware logic mapping for crossbar nano-architectures
M Zamani, MB Tahoori
16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 317-322, 2011
142011
Online missing/repeated gate faults detection in reversible circuits
M Zamani, MB Tahoori
2011 IEEE international symposium on defect and fault tolerance in VLSI and …, 2011
132011
Online multiple fault detection in reversible circuits
N Farazmand, M Zamani, MB Tahoori
2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI …, 2010
102010
A transient error tolerant self-timed asynchronous architecture
M Zamani, MB Tahoori
2010 15th IEEE European Test Symposium, 88-93, 2010
52010
Reliable logic mapping on Nano-PLA architectures
M Zamani, MB Tahoori
Proceedings of the great lakes symposium on VLSI, 107-110, 2012
42012
Self-timed nano-PLA
M Zamani, MB Tahoori
2011 IEEE/ACM International Symposium on Nanoscale Architectures, 78-85, 2011
42011
Variation-immune quasi delay-insensitive implementation on nano-crossbar arrays
M Zamani, MB Tahoori
Proceedings of the 21st edition of the great lakes symposium on Great lakes …, 2011
32011
Variation Tolerance for Nano-PLA Architectures
M Zamani, M B. Tahoori
20th IEEE North Atlantic Test Workshop (NATW), 2011
32011
An efficient fault simulator for QDI asynchronous circuits
AM Rahmani, AA Salehpour, M Zamani, S Mohammadi, H Pedram
2008 4th Southern Conference on Programmable Logic, 99-104, 2008
22008
Apparatus and method of clock shaping for memory
M Zamani, B Zafar, V Narayanan
US Patent 10,163,474, 2018
12018
Reliable Design for Crossbar Nano-architectures
M Zamani, MB Tahoori
Modeling, Methodologies and Tools for Molecular and Nano-scale …, 2017
12017
Testable Design of Template based QDI Asynchronous Circuits
M Zamani, M Najibi, H Pedram
Proceedings of IEEE East-West Design & Test Symposium, 2007
12007
Asynchronous behavior related Retiming in Gated-Clock GALS systems
S Farrokhi, M Zamani, H Pedram, M Sedighi
Proc. Int. East-West Design and Test Symp, 515-521, 2007
12007
Apparatus and method of clock shaping for memory
M Zamani, B Zafar, V Narayanan
US Patent App. 16/655,034, 2020
2020
Apparatus and method of clock shaping for memory
M Zamani, B Zafar, V Narayanan
US Patent 10,490,242, 2019
2019
Apparatus and method for employing mutually exclusive write and read clock signals in scan capture mode for testing digital interfaces
B Zafar, R Vattikonda, D Lu, V Narayanan, M Zamani, J Fang
US Patent App. 15/263,059, 2018
2018
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