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Jeremy Levitt
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Validity checking for combinations of theories with equality
C Barrett, D Dill, J Levitt
Formal Methods in Computer-Aided Design: First International Conference …, 1996
2731996
A decision procedure for an extensional theory of arrays
A Stump, CW Barrett, DL Dill, J Levitt
Proceedings 16th Annual IEEE Symposium on Logic in Computer Science, 29-37, 2001
2262001
A decision procedure for bit-vector arithmetic
CW Barrett, DL Dill, JR Levitt
Proceedings of the 35th Annual Design Automation Conference, 522-527, 1998
1891998
A software-hardware cosynthesis approach to digital system simulation
KA Olukotun, R Helaihel, J Levitt, R Ramirez
IEEE Micro 14 (4), 48-58, 1994
781994
A general method for compiling event-driven simulations
RS French, MS Lam, JR Levitt, K Olukotun
Proceedings of the 32nd Annual ACM/IEEE Design Automation Conference, 151-156, 1995
761995
Measure of analysis performed in property checking
JR Levitt, C Gauthron, CMR Ho, PF Yeung, KC Mulam, R Sathianathan
US Patent 6,848,088, 2005
55*2005
Functional test selection based on unsupervised support vector analysis
O Guzey, LC Wang, J Levitt, H Foster
Proceedings of the 45th annual Design Automation Conference, 262-267, 2008
502008
A scalable formal verification methodology for pipelined microprocessors
J Levitt, K Olukotun
Proceedings of the 33rd annual Design Automation Conference, 558-563, 1996
471996
Verifying correct pipeline implementation for microprocessors
Levitt, Olukotun
1997 Proceedings of IEEE International Conference on Computer Aided Design …, 1997
451997
Selection of initial states for formal verification
JAG Seawright, R Sathianathan, CG Gauthron, JR Levitt, KC Mulam, ...
US Patent 7,454,324, 2008
432008
Formal verification techniques for digital systems
JR Levitt
stanford university, 1999
311999
Increasing the efficiency of simulation-based functional verification through unsupervised support vector analysis
O Guzey, LC Wang, JR Levitt, H Foster
IEEE transactions on computer-aided design of integrated circuits and …, 2009
212009
Reuse of learned information to simplify functional verification of a digital circuit
J Levitt, C Gauthron, C Barrett, L Widdoes
US Patent App. 10/340,555, 2007
212007
Automatic assume guarantee analysis for assertion-based formal verification
D Wang, J Levitt
Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005
182005
Measure of analysis performed in property checking
JR Levitt, C Gauthron, CR Ho, PF Yeung, KC Mulam, R Sathianathan
US Patent 7,318,205, 2008
132008
Using formal techniques to verify system on chip reset schemes
K Liu, P Yang, J Levitt, M Berman, M Eslinger
Proc. DVCon, 2013
102013
Clock model for formal verification of a digital circuit description
JAG Seawright, JR Levitt, C Gauthron
US Patent 7,487,483, 2009
92009
A General Method for Compiling Event-Driven Simulations. 32nd ACM
R French, M Lam, J Levitt, K Olukotun
IEEE Design Automation Conference 10 (217474.217522), 1995
91995
Measure of analysis performed in property checking
JR Levitt, C Gauthron, CMR Ho, PF Yeung, KC Mulam, R Sathianathan
US Patent 8,418,121, 2013
52013
FREEDOM, JUSTICE, EQUALITY AND FRATERNITY ARE THE FOUR CARDINAL PRINCIPLES OF FREEMASONRY.
JR Levitt
Education 107 (4), 1987
51987
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Artikelen 1–20